DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 18

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
10.4.3 Input port swapping
Table 9.
The LVDS DDR receiver block internally maps the incoming LVDS data bus into two
buses with a single data rate (Figure 7).
These two buses can be swapped internally using bit LDAB_SWAP of register
LD_CNTRL (see Table 60 and Figure 8).
Internal LVDS bus
LDI[15]P,N
LDI[14]P,N
LDI[13]P,N
LDI[12]P,N
LDI[11]P,N
LDI[10]P,N
LDI[9]P,N
LDI[8]P,N
LDI[7]P,N
LDI[6]P,N
LDI[5]P,N
LDI[4]P,N
LDI[3]P,N
LDI[2]P,N
LDI[1]P,N
LDI[0]P,N
Fig 7.
A0
LVDS DDR receiver mapping LDAB SWAP = 0
B0
Input LVDS bus swapping
A1
B1
A2
Rev. 03 — 2 July 2012
B2
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
A3
External LVDS bus
(WORD_SWAP = 0)
LD[15]P,N
LD[14]P,N
LD[13]P,N
LD[12]P,N
LD[11]P,N
LD[10]P,N
LD[9]P,N
LD[8]P,N
LD[7]P,N
LD[6]P,N
LD[5]P,N
LD[4]P,N
LD[3]P,N
LD[2]P,N
LD[1]P,N
LD[0]P,N
B3
LD[15..0]P/N
LCLKP/N
RECEIVER
LVDS
PB[15..0]
PA[15..0]
LCLK
DAC1617D1G0
A0
B0
External LVDS bus
(WORD_SWAP = 1)
LD[0]P,N
LD[1]P,N
LD[2]P,N
LD[3]P,N
LD[4]P,N
LD[5]P,N
LD[6]P,N
LD[7]P,N
LD[8]P,N
LD[9]P,N
LD[10]P,N
LD[11]P,N
LD[12]P,N
LD[13]P,N
LD[14]P,N
LD[15]P,N
to DAC A
to DAC B
A1
B1
A2
B2
© IDT 2012. All rights reserved.
001aan393
A3
B3
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