DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 51

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 23.
Default values are shown highlighted.
Table 24.
Default values are shown highlighted.
Table 25.
Default values are shown highlighted.
DAC1617D1G0 3
Preliminary data sheet
Bit
1 to 0
Bit
7
6
5
4 to 3
2 to 1
0
Address
04h
05h
Symbol
INTERPOLATION[1:0]
Symbol
PLL_BP
PLL_BUF_PD
PLL_PLL_PD
PLL_DIV[1:0]
PLL_PHASE[1:0]
PLL_OSC_PD
Register TXCFG (address 01h) bit description
Register PLLCFG (address 02h) bit description
NCO frequency registers (address 04h to 08h) bit description
Register
FREQNCO_B0 7 to 0
FREQNCO_B1 7 to 0
Bit
Symbol
FREQ_NCO[7:0]
FREQ_NCO[15:8]
Access
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Value
00
01
10
11
Value
0
1
0
1
0
1
00
01
10
11
00
01
10
11
0
1
…continued
Access Value
R/W
R/W
Description
interpolation
Description
PLL bypass
PLL test buffer control
PLL and CKGEN control
PLL divider factor
PLL phase shift
PLL oscillator output power-down
no interpolation
2 interpolation
4 interpolation
8 interpolation
DAC clock generated by PLL
DAC clock provided via external pins CLKN and
CLKP (PLL bypass mode)
Power-down mode
enabled
Power-down mode
enable
f
f
f
undefined
0 degrees phase shift of f
120 degrees phase shift of f
240 degrees phase shift of f
240 degrees phase shift of f
Power-down mode
enabled
s
s
s
-
-
= 4  f
= 8  f
= 2  f
data
data
Description
NCO frequency (two’s complement
coding)
least significant 8 bits for the NCO
frequency setting
intermediate 8 bits for the NCO
frequency setting
DAC1617D1G0
s
s
s
s
© IDT 2012. All rights reserved.
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