DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet

DAC1617D1G0HN

Manufacturer Part Number

DAC1617D1G0HN

Description

Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating

Manufacturer

IDT [Integrated Device Technology]

Datasheet

1.DAC1617D1G0HN.pdf (78 pages)

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1. General description

2. Features and benefits

The DAC1617D1G0 is a high-speed 16-bit dual channel Digital-to-Analog Converter

(DAC) with selectable 2, 4 and 8 interpolation filters. The device is optimized for

multi-carrier and broadband wireless transmitters at sample rates of up to 1 Gsps.

Supplied from a 3.3 V and a 1.8 V source, the DAC1617D1G0 integrates a differential

scalable output current up to 34 mA.

The Serial Peripheral Interface (SPI) provides full control of the DAC1617D1G0.

The DAC1617D1G0 integrates a Low Voltage Differential Signaling (LVDS) Double Data

Rate (DDR) receiver interface, with an on-chip 100  termination. The LVDS DDR

interface accepts a multiplex input data stream such as interleaved or folded. An internal

LVDS input auto-calibration ensures the robustness and stability of the interface.

Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. A

40-bit Numerically Controlled Oscillator (NCO) sets the mixer frequency. High resolution

internal gain, phase and offset control provide outstanding image and Local Oscillator

(LO) signal rejection at the system analog modulator output.

An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at

the DAC output.

Multiple device synchronization allows synchronization of the outputs of multiple DAC

devices. MDS guarantees a maximum skew of one output clock period between several

devices.

The DAC1617D1G0 includes a very low noise capacitor-free integrated Phase-Locked

Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.

The DAC1617D1G0 is available in an HVQFN72 package (10 mm  10 mm).



DAC1617D1G0

Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8

interpolating

Rev. 03 — 2 July 2012

Dual-channel 16-bit resolution

1 Gsps maximum update rate

Selectable 2, 4 and 8 interpolation

filters

Very low noise capacitor-free integrated

Phase-Locked Loop (PLL)



Synchronization of multiple DAC

devices

3-wire or 4-wire mode SPI interface

Differential scalable output current from

8.1 mA to 34 mA

External analog offset control

(10-bit auxiliary DACs)

Preliminary data sheet

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