DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 23

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
The compensation delay time (t
Bit CAL_CNTRL of the MAIN_CNTRL register (see Table 54) enables the switching
between automatic tuning and manual tuning.
In Automatic tuning mode, the external LVDS data and clock signals are generated using
the same reference clock (inside the FPGA). The LDCLK clock is similar to a data bit that
toggles each time (the rising edge and falling edge of the LDCLK and LVDS data occur at
the same time). In automatic tuning, the internal compensation delay time (t
automatically to compensate the internal DAC1617D1G0 delay time optimally.
The timing requirement in automatic tuning mode is defined in Figure 15 and in Table 5.
Fig 14. LVDS DDR demux timing (LVDS A and B paths not swapped; LDAB_SWAP = 0)
Fig 15. Timing requirement automatic tuning
t
t
sk(min)
sk(max)
LVDS data
LVDS clock
= minimum skew time
= maximum skew time
LDCLKNcp
LDCLKPcp
LDCLKN
LDCLKP
LD[i]N
LD[i]P
LDB[i]
LDA[i]
Rev. 03 — 2 July 2012
D
D
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
n − 1
n − 1
t
[i]
[i]
cmp
cmp
t
D
sk(min)
n
in Figure 14) can be tuned automatically or manually.
V
[i]
V
IH
IL
D
D
n + 1
D
n + 1
n
[i]
t
V
V
sk(max)
[i]
[i]
IH
IL
D
n + 2
DAC1617D1G0
[i]
D
D
001aan400
n + 2
n + 3
[i]
[i]
001aan833
© IDT 2012. All rights reserved.
cmp
) is defined
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