DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 25

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
10.4 Clock input
The DAC1408D650 has one differential clock input, CLKINN/CLKINP.
The DAC1408D650 can operate with a clock frequency up to 312.5 MHz or up to
650 MHz if the internal PLL is bypassed. The clock input can be LVDS (see
it can also be interfaced with CML (see
During the reset phase (RESET_N asserted), the clock must be stable and running. This
ensures a proper reset of the complete device.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
Fig 16. LVDS clock configuration
Fig 17. Interfacing CML to LVDS
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
CML
Rev. 02 — 11 August 2010
Z = 50 Ω
Z = 50 Ω
LVDS
Z = 50 Ω
Z = 50 Ω
Zdiff =
100 Ω
100 nF
100 nF
V
DDA(1V8)
AGND
Figure
1.1 kΩ
2.2 kΩ
Zdiff =
100 Ω
CLKP
CLKN
55 Ω
55 Ω
17).
100 nF
CLKN
CLKP
001aah021
LVDS
DAC1408D650
001aah020
LVDS
© NXP B.V. 2010. All rights reserved.
Figure
16) but
25 of 98