DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 14
![no-image](/images/no-image-200.jpg)
DAC1408D650C1
Manufacturer Part Number
DAC1408D650C1
Description
Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.DAC1408D650C1.pdf
(98 pages)
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NXP Semiconductors
DAC1408D650
Preliminary data sheet
10.2.3 Comma detection and word align
The lane processing makes use of the SYNC-patterns to synchronize the datastream,
determine the initial running disparity and extract the 10-bit word from the incoming
datastream (word-alignment).
The SYNC signal is also used during normal operation by the DAC1408D650 to request a
link re-initialization. This occurs when the 8b/10b module loses synchronization.
The SYNC_OUT signal conforms to LVDS signaling. Its common mode voltage and its
differential peak-to-peak amplitude (see
SYNC_OUT is synchronous with the frame clock.
Table 7.
[1]
This stage monitors the datastream for code characters (comma detection), decodes the
words to bytes (octets) and performs optional character replacement as part of frame/lane
alignment monitoring and correction. This module provides the required control signals to
the RX-controller and ILA.
This module decodes the 10-bit words into 8-bit words (octets). The decoding table is
specified in the IEEE Std.802.3-2005 specification. During decoding, the disparity is
calculated according to the disparity rules mentioned in the same specification IEEE
Std.802.3-2005. When the disparity counter is more than +2 or less than −2, an error will
be generated.
The following comma symbols are detected during data transmission irrespective of the
running disparity:
Symbol Parameter
t
d
Fig 7.
C = guaranteed by characterization.
SYNC_OUT timing
delay time
SYNC_OUT timing
/K/=K28.5
/F/=K28.7
/A/=K28.3
/R/=K28.0
/Q/=K28.4
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
Conditions
frame clock to sync
Rev. 02 — 11 August 2010
SYNC_OUT
t
FS_R(min)
CLK
t
FS_R(max)
Table
78) can be programmed using registers.
Test
C
[1]
Min
<tbd>
001aak165
DAC1408D650
Typ
-
© NXP B.V. 2010. All rights reserved.
Max
<tbd>
Unit
ns
14 of 98
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