DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 18

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges will reach each of the
DACs at different times.
The worst case clock skew is given by
trace delay and also the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by
Fig 10. Clock skew case 1: Master is farthest
slave 1 clock
slave 2 clock
master clock
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
ref clock
Rev. 02 — 11 August 2010
PH03
PH02
δt
PH01
1
TDAC
=
PH01 PH03
–
DAC1408D650
, where PH0x represents the
Δt
001aal072
=
© NXP B.V. 2010. All rights reserved.
TDAC δt
–
18 of 98
1
.