DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 15

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
10.2.5.1 Single device operation
10.2.4 Descrambler
10.2.5 Interlane alignment
The following flags are also triggered according to the following definitions:
DAC1408D650 supports character replacement whatever the state of the descrambler.
When scrambling is not active, the received K28.3 /A/ or K28.7 /F/ will be replaced by the
previous sample. When scrambling is active, the corresponding data octet D28.3 (0xC) or
D28.7 (0xFC) will be used.
The used descrambler is the 16-bit parallel self-synchronous descrambler based on the
polynomial
This feature removes strict PCB design skew compensation between the lanes.
This module handles the alignment of the four data streams. Because of interlane skew
and each PLL per lane concept, these alignment characters may be received at different
times by the receivers. After the synchronization period, the lock signal will be high. This
enables the receiving of K28.3 /A/ characters.
The /A/-characters provided in the initial alignment sequence are then used to align the
four data streams. With the bit field sel_ila (two bits) (refer to
register (address 07h) bit
use the 1st /A/ symbol, “01” ⇒ use the 2nd /A/ symbol, “10” ⇒ use the 3rd /A/ symbol,
“11” ⇒ use the 4th /A/ symbol) during the initial lane alignment. When all receivers have
received their first selected /A/, they start propagating the received data to the frame
assembly module at the same point in time.
This module can compensate up to +7/−7 frame clock period misalignment between the
lanes.
When initial lane alignment is not supported, the manual alignment mode can be used.
After the initial ILA sequence, the lane alignment monitoring starts. When a K28.3 /A/
symbol is received among the user data:
A flag is sent to the control interface to reflect detected commas in registers.
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VALID: a code group that is found in the column of the 8b/10b decoding tables
according to the current running disparity.
DISPARITY ERROR: The received code group exists in the 8b/10b decoding table,
but is not found in the proper column according to the current running disparity.
NOT-IN-TABLE ERROR: The received code group is not found in the 8b/10b
decoding table for either disparity.
INVALID: a code group that either shows a disparity error or that does not exist in the
8b/10b decoding table.
its position is compared to the value of the alignment monitor counter
if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
1
+
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
x
All information provided in this document is subject to legal disclaimers.
14
+
x
15
Rev. 02 — 11 August 2010
. This processing can be turned off.
description”), one can select the used K28.3 /A/ symbol (“00” ⇒
DAC1408D650
Table 87 “ILA_CNTRL
© NXP B.V. 2010. All rights reserved.
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