AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 88

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Table 41. V-Sequence (VSEQ) Registers
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Data
Bits
[0]
[1]
[5:2]
[9:6]
[13:10]
[15:14]
[19:16]
[23:20]
[25:24]
[12:0]
[25:13]
[23:0]
[24]
[25]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
Default
Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Update
Type
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
Mnemonic
CLPOBPOL
PBLKPOL
HOLD
VMASK_EN
CONCAT_GRP
VREP_MODE
LASTREPLEN_EN
LASTTOG_EN
HBLK_MODE
HDLENE
HDLENO
VSGPATSEL
HDLENE_13
HDLENO_13
VPOL_A
VPOL_B
VPOL_C
VPOL_D
GROUPSEL_0
GROUPSEL_1
Rev. C | Page 88 of 92
Description
CLPOB start polarity.
PBLK start polarity.
1: Enable HOLD function for each VPAT group (A, B, C, D).
1: Enable FREEZE/RESUME for each VPAT group (A, B, C, D).
Combine multiple VPAT groups together in one sequence. Set register equal
to 0x01 to enable.
Defines V-alternation repetition mode.
00: Single pattern alternation for all groups.
01: Two pattern alternation for all groups.
10: Three-pattern alternation for Group A. Groups B, C, and D
11: Four-pattern alternation for Group A. Two-pattern alternation
Enable use of last repetition counter for last repetition length of each group.
Enable the fifth toggle position for all V-signals in each group.
Selection of HBLK modes:
00: HBLK Mode 0 (normal six-toggle operation).
01: HBLK Mode 1.
10: HBLK Mode 2. (Address 0x19 to Address 0x1E operate differently.)
11: Test only, do not access.
HD line length for even lines.
HD line length for odd lines.
Selects which two toggle positions are used by each V-output when they
are configured as VSG pulses (Miscellaneous Register Address 0x1C, fixed
register area):
0: Use Toggle 1, Toggle 2.
1: Use Toggle 3, Toggle 4.
HD length Bit 13 for even lines when 14-bit H-counter is enabled.
HD length Bit 13 for odd lines when 14-bit H-counter is enabled.
Starting polarities for each V-output signal (Group A).
Starting polarities for each V-output signal (Group B).
Starting polarities for each V-output signal (Group C).
Starting polarities for each V-output signal (Group D).
Select which group each XV1 to XV12 signal is assigned to:
00: Group A.
01: Group B.
10: Group C.
11: Group D.
[1:0]: XV1.
[3:2]: XV2.
…
[23:22]: XV12.
Select which group each XV13 to XV24 signal is assigned to:
00: Group A.
01: Group B.
10: Group C.
11: Group D.
[1:0]: XV13.
[3:2]: XV14.
…
[23:22]: XV24.
follow pattern {0, 1, 1, 0, 1, 1…}.
for Groups B, C, and D.