AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 75

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

COMPLETE REGISTER LISTING
When an address contains fewer than 28 data bits, all remaining bits must be written as 0s.
Table 29. AFE Registers
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x0D
Table 30. Miscellaneous Registers
Address
0x10
0x11
0x12
0x13
Data
Bits
[1:0]
[2]
[3]
[4]
[5]
[6]
[0]
[1]
[2]
[3]
[0]
[23:0]
[2:0]
[9:0]
[9:0]
[0]
Data
Bits
[0]
[0]
[0]
[4:1]
[0]
[1]
Default
Value
0
0
0
0
1
0
Default
Value
3
1
0
0
0
0
0
0
0
1
0
FFFFFF
0
F
1EC
0
Update
Type
SCK
VD
SCK
SCK
Update
Type
SCK
SCK
SCK
SCK
VD
VD
VD
VD
Mnemonic
SW_RST
OUTCONTROL
RSTB_EN
TEST
SYNCENABLE
SYNCPOL
Mnemonic
STANDBY
CLPENABLE
CLPSPEED
FASTUPDATE
PBLK_LVL
DCBYP
DOUTDISABLE
DOUTLATCH
GRAY_EN
TEST
TEST
TEST
CDSGAIN
VGAGAIN
CLAMPLEVEL
CLIDIVIDE
Rev. C | Page 75 of 92
Description
Standby modes:
0: Normal operation.
1: Standby1 mode.
2: Standby2 mode.
3: Standby3 mode.
0: Disable OB clamp.
1: Enable OB clamp.
0: Select normal OB clamp settling.
1: Select fast OB clamp settling.
0: Ignore CDS gain.
1: Very fast clamping when CDS gain is updated.
0: Blank data outputs to 0 during PBLK.
1: Blank data outputs to programmed clamp level during PBLK.
0: Enable input dc restore circuit during PBLK.
1: Disable input dc restore circuit during PBLK.
0: Data outputs are driven.
1: Data outputs are three-stated.
0: Latch data outputs using the rising edge of DOUTPHASEP
1: Output latch is transparent.
1: Enable gray encoding of the digital data outputs.
Set to 0.
Do not access, or set to 0.
Do not access, or set to 0xFFFFFF.
CDS gain setting:
0: −3 dB.
4: 0 dB.
6: +3 dB.
7: +6 dB.
All other values are invalid.
VGA gain, 6 dB to 42 dB (0.035 dB per step).
Optical black clamp level, 0 to 1023 LSB (1 LSB per step).
0: No division of CLI.
1: Divide CLI input frequency by 2.
(DOUTPHASEP register setting).
Description
Software reset. Bit self-clears to 0 when a reset occurs.
1: Reset Address 0x00 to Address 0xFF to default values.
0: Make all outputs dc inactive.
1: Enable outputs at next VD edge.
1: Configure SYNC pin as RSTB input signal.
Test mode only. Must be set to 0.
1: External synchronization enable (configures Pin D3 as an
input).
SYNC active polarity.
AD9992