AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 67

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

(PIXEL COUNTER)
(PIXEL COUNTER)
STANDBY MODE OPERATION
The AD9992 contains three standby modes to optimize the overall
power dissipation in a particular application. Bits [1:0] of Address
0x00 control the power-down state of the device:
• STANDBY [1:0] = 0 = normal operation (full power)
• STANDBY [1:0] = 1 = Standby1 mode
• STANDBY [1:0] = 2 = Standby2 mode
• STANDBY [1:0] = 3 = Standby3 mode (lowest power)
Table 27 summarizes the operation of each power-down mode.
The OUTCONTROL register takes priority over the Standby1
and Standby2 modes in determining the digital output states,
but Standby3 mode takes priority over OUTCONTROL.
Standby3 has the lowest power consumption and even shuts
down the crystal oscillator circuit between CLI and CLO.
Therefore, if CLI and CLO are being used with a crystal to
generate the master clock, this circuit is powered down and
there is no clock signal. When returning from Standby3 mode
to normal operation, the timing core must be reset at least
500 μs after the STANDBY register is written to. This allows
sufficient time for the crystal circuit to settle.
H-COUNTER
H-COUNTER
HD
VD
HD
VD
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 36 PIXELS OF PIXEL 0 LOCATION.
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 36 PIXELS OF PIXEL 0 LOCATION.
X
X
X
X
X
X
X
X
N – 35
X
N – 34
X
N – 35
N – 33
Figure 78. Toggle Position Inhibited Area—Master Mode
N – 34
N – 32
Figure 79. Toggle Position Inhibited Area—Slave Mode
N – 33
N – 32
N – 13
N – 12
Rev. C | Page 67 of 92
N – 13
N – 11
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
N – 12
N – 10
N – 11
N – 9
The vertical outputs can also be programmed to hold a specific
value during the Standby3 mode by using Address 0x26. This
register is useful during power-up if different polarities are
required by the V-driver and CCD to prevent damage when VH
and VL areas are applied. The polarities for Standby1 mode and
Standby2 mode are also programmable, using Address 0x25.
OUTCONTROL = low also uses the same polarities programmed
for Standby1 and Standby2 modes in Address 0x25. The GPO
polarities are programmable using Address 0x27.
Note that the GPO outputs are high-Z by default at power-up
until Address 0x78 is used to select them as outputs.
CLI FREQUENCY CHANGE
If the input clock CLI is interrupted or changed to a different
frequency, the timing core must be reset for proper operation.
After the CLI clock settles to the new frequency, or the previous
frequency is resumed, write 0 and then 1 to the TGCORE_RSTB
register (Address 0x14). This guarantees that the timing core
operates properly.
N – 10
N – 8
N – 7
N – 9
N – 6
N – 8
N – 5
N – 7
N – 4
N – 6
N – 3
N – 5
N – 2
N – 4
N – 1
N – 3
H-COUNTER
N – 2
RESET
N
N – 1
0
H-COUNTER
RESET
1
N
2
0
AD9992
3
1
4
2