AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 62

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9992 signal processing chain is shown in Figure 72.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.2 V, making it compatible with the 1.8 V core
supply voltage of the AD9992. The dc restore switch is active
during the SHP sample pulse time.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large-signal swings from the CCD input
(see the Analog Preblanking section). Bit 6 of AFE Register
Address 0x00 controls whether the dc restore is active during the
PBLK interval.
Analog Preblanking
During certain CCD blanking or substrate clocking intervals,
the CCD input signal to the AD9992 can increase in amplitude
beyond the recommended input range. The PBLK signal can be
used to isolate the CDS input from large-signal swings. While
PBLK is active (low), the CDS input is internally shorted to ground.
0.1µF
CCDIN
CLI
1.2V
PBLK
1
S1 IS NORMALLY CLOSED; S2 IS NORMALLY OPEN.
S1
DC RESTORE
1
S2
1
SHP SHD
REGISTER
CDS GAIN
GENERATION
SHP
CDS
PRECISION
TIMING
SHD
DOUTPHASE
–3dB, 0dB,
+3dB, +6dB
SHP
PBLK (WHEN DCBYP = 1)
Figure 72. Analog Front-End Functional Block Diagram
REGISTER
VGA GAIN
6dB ~ 42dB
VGA
CLPOB PBLK
GENERATION
TIMING
V-H
Rev. C | Page 62 of 92
DAC
DIGITAL
FILTER
OPTICAL BLACK
Note that, because the CDS input is shorted during PBLK, the
CLPOB pulse should not be used during the same active time as
the PBLK pulse.
Correlated Double Sampler (CDS)
The CDS circuit samples each CCD pixel twice to extract the video
information and to reject low frequency noise. The timing
shown in Figure 19 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and data level of the CCD signal, respectively. The placement
of the SHP and SHD sampling edges is determined by the setting
of the SHPLOC and SHDLOC registers located at Address 0x37.
Placement of these two clock signals is critical for achieving the
best performance from the CCD.
The CDS gain is variable in three steps by using the AFE
Address 0x04: −3 dB, 0 dB (default), and +3 dB. Improved noise
performance results from using the +3 dB setting, but the input
range is reduced (see the Analog Specifications section).
INTERNAL
CLAMP
0.1µF 0.1µF
REFB
0.4V
12-BIT
V
ADC
REF
2V FULL SCALE
REFT
1.4V
CLAMP LEVEL
DOUTPHASE
REGISTER
CLI
CLPOB
OUTPUT
LATCH
DELAY
FIXED
DATA
PBLK
BLANK TO
ZERO OR
CLAMP LEVEL
MODE
DCLK
1
0
DCLKINV
AD9992
12
VD
HD
DCLK
DOUT