AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 6

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
TIMING SPECIFICATIONS
C
Table 4.
Parameter
MASTER CLOCK (See Figure 15)
SLAVE MODE SPECIFICATIONS (See Figure 76)
AFE CLPOB PULSE WIDTH (See Figure 22 and Figure 32)
AFE SAMPLE LOCATION (See Figure 16 and Figure 19)
DATA OUTPUTS (See Figure 20 and Figure 21)
SERIAL INTERFACE (See Figure 83)
INHIBIT REGION FOR SHP AND SHD WITH RESPECT TO H-CLOCK
1
2
Parameter is programmable.
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
L
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal Pixel Position 0
VD Falling Edge to HD Falling Edge in Slave Mode
HD Edge to CLI Rising Edge (Only Valid if OSC_RSTB = LO)
HD Edge to CLO Rising Edge (Only Valid if OSC_RSTB = HI)
Inhibit Region for SHP Edge Location
SHP Sample Edge to SHD Sample Edge
Output Delay from DCLK Rising Edge
Inhibited Area for DOUTPHASE Edge Location
Pipeline Delay from SHP/SHD Sampling to DOUT
Maximum SCK Frequency (Must Not Exceed CLI Frequency)
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
EDGE PLACEMENT (see Figure 19) for H*POL = 1
RETIME = 0, MASK = 0
RETIME = 0, MASK = 1
RETIME = 1, MASK = 0
RETIME = 1, MASK = 1
= 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, f
1
1, 2
Rev. C | Page 6 of 92
Symbol
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
SCLK
CONV
CLIDLY
VDHD
HDCLI
HDCLO
SHPINH
S1
OD
DOUTINH
LS
LH
DS
DH
SHDINH
SHDINH
SHPINH
SHPINH
CLI
= 40 MHz, unless otherwise noted.
Min
25
10
0
3
3
48
2
11
SHDLOC + 1
40
10
10
10
10
H*NEGLOC – 15
H*POSLOC – 15
H*NEGLOC – 15
H*POSLOC – 15
Typ
12.5
6
20
12.5
1
16
Max
15
VD period − 5 ×
t
t
t
63
SHDLOC + 15
H*NEGLOC – 0
H*POSLOC – 0
H*NEGLOC – 0
H*POSLOC – 0
CONV
CONV
CONV
− 2
− 2
Unit
ns
ns
ns
ns
ns
ns
Edge location
Pixels
ns
ns
Edge location
Cycles
MHz
ns
ns
ns
ns
Edge location
Edge location
Edge location
Edge location