AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 68

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Table 27. Standby Mode Operation (Standby Polarities for XV, XSUBCK, GPO Outputs Are Programmable)
I/O Block
AFE
Timing Core
CLO Oscillator
CLO
H1
H2
H3
H4
H5
H6
H7
H8
HL
RG
VD
HD
DCLK
DOUT
XV1 to XV24
XSUBCK
GPO1 to GPO8
1
2
3
4
To exit Standby3, write 00 to STANDBY (Address 0x00, Bits [1:0]), and then reset the timing core after 500 μs to guarantee proper settling of the oscillator and external crystal.
Standby3 mode takes priority over OUTCONTROL for determining the output polarities.
These polarities assume OUTCONTROL = high because OUTCONTROL = low takes priority over Standby1 and Standby2.
Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).
Standby3 (Default)
Off
Off
Off
Low
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Low
Low
Low
Low
Low
Low
Low
1, 2
OUTCONTROL = Low
No change
No change
No change
No change
Low
High
Low
High
Low
High
Low
High
Low
Low
VDHDPOL value
VDHDPOL value
Running
Low
Low
Low
Low
Rev. C | Page 68 of 92
2
Standby2
Off
Off
Off
Low
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
VDHDPOL value
VDHDPOL value
Low
Low
Low
Low
Low
3, 4
Standby1
Only REFT, REFB on
On
On
Running
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Running
Running
Running
Low
Low
Low
Low
3, 4