AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 5

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

ANALOG SPECIFICATIONS
AVDD = 1.8 V, f
Table 3.
Parameter
CDS
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
ADC
VOLTAGE REFERENCE
SYSTEM PERFORMANCE
Allowable CCD Reset Transient
CDS Gain Accuracy
Maximum Input Range Before Saturation
Allowable OB Pixel Amplitude (See
Gain Control Resolution
Gain Monotonicity
Gain Range
Clamp Level Resolution
Clamp Level
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Integral Nonlinearity (INL)
Full-Scale Input Voltage
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
Gain Accuracy
Peak Nonlinearity, 1.0 V Input Signal
Total Output Noise
Power Supply Rejection (PSR)
−3.0 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
0 dB CDS Gain (Default)
+6 dB CDS Gain
Low Gain (VGA Code 15, Default)
Maximum Gain (VGA Code 1023)
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
Low Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
CLI
= 40 MHz, typical timing specifications, T
Figure 2
)
Min
−3.3
−0.5
2.4
5.0
−100
−50
12
−1.0
5.8
41.9
Guaranteed
Guaranteed
Typ
0.5
−2.8
0
2.9
5.5
1.4
1.0
0.7
0.5
1024
6.3
42.4
1024
0
255
±0.5
1
2.0
1.4
0.4
6.3
42.4
0.1
0.5
50
Rev. C | Page 5 of 92
MIN
to T
MAX
Max
0.8
−2.3
+0.5
3.4
6.0
+200
+100
+1.0
4
6.8
42.9
0.2
, unless otherwise noted.
Unit
V
dB
dB
dB
dB
V p-p
V p-p
V p-p
V p-p
mV
mV
Steps
dB
dB
Steps
LSB
LSB
Bits
LSB
LSB
V
V
V
dB
dB
%
LSB rms
dB
Test Conditions/Comments
The limit is the lower of AVDD + 0.2 V or 2.2 V.
VGA gain = 6.3 dB (Code 15, default value).
VGA gain = 6.3 dB (Code 15, default value).
Measured at ADC output.
Includes entire signal chain.
0 dB CDS gain.
Gain = (0.0358 × Code) + 5.76 dB.
6 dB VGA gain, 0 dB CDS gain applied.
AC-grounded input, 6 dB VGA gain applied.
Measured with step change on supply.
AD9992