CY7C1471BV33_11 CYPRESS [Cypress Semiconductor], CY7C1471BV33_11 Datasheet - Page 27

• Manufacturer Part Number: CY7C1471BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 6
Notes
Document Number: 001-15029 Rev. *E
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
COMMAND
ADDRESS
ADV/LD
BW
shows NOP, STALL and DESELECT Cycles waveform.
CEN
CLK
[A:D]
WE
DQ
CE
WRITE
D(A1)
A1
1
1
is LOW, CE
D(A1)
Q(A2)
READ
A2
2
2
(continued)
is HIGH, and CE
Figure 6. NOP, STALL, and DESELECT Cycles
STALL
3
3
Q(A2)
is LOW. When CE is HIGH, CE
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
READ
Q(A3)
A3
4
DON’T CARE
WRITE
D(A4)
A4
Q(A3)
5
[25, 26, 27]
1
is HIGH, CE
STALL
UNDEFINED
6
2
is LOW or CE
D(A4)
NOP
7
3
Q(A5)
READ
is HIGH.
A5
8
t DOH
DESELECT
Q(A5)
9
t CHZ
CONTINUE
DESELECT
10
Page 27 of 35
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