CY7C1471BV33_11 CYPRESS [Cypress Semiconductor], CY7C1471BV33_11 Datasheet - Page 20

• Manufacturer Part Number: CY7C1471BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Identification Register Definitions
Scan Register Sizes
Identification Codes
Note
Document Number: 001-15029 Rev. *E
Revision number (31:29)
Device depth (28:24)
Architecture/memory type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Instruction
Bypass
ID
Boundary scan order – 165FBGA
Boundary scan order – 209BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Instruction Field
Instruction
Register Name
[14]
CY7C1471BV33
00000110100
(2 M × 36)
001001
100100
01011
000
1
Code
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
000
001
010
100
101
011
110
111
Captures I/O ring contents. Places the boundary scan register between TDI
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM outputs to High-Z state. This instruction is not
1149.1-compliant.
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
Do not use: This instruction is reserved for future use.
and TDO. Does not affect SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do not use: This instruction is reserved for future use.
Do not use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operations.
CY7C1473BV33
00000110100
(4 M × 18)
001001
010100
Bit Size (x36)
01011
000
1
32
71
3
1
–
CY7C1475BV33
00000110100
(1 M × 72)
001001
110100
01011
000
1
Bit Size (x18)
Description
32
52
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
Enables unique identification of SRAM
vendor
Indicates the presence of an ID
register
3
1
–
Description
Bit Size (x72)
110
32
Page 20 of 35
3
1
–
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