CY7C1471BV33_11 CYPRESS [Cypress Semiconductor], CY7C1471BV33_11 Datasheet - Page 19

• Manufacturer Part Number: CY7C1471BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

TAP AC Switching Characteristics
Over the Operating Range
TAP Timing
Notes
Document Number: 001-15029 Rev. *E
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
12. t
13. Test conditions are specified using the load in TAP AC Test Conditions. t
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
CS
Parameter
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
Test M ode Select
Test Data-Out
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
TMs hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Test Data-In
Test Clock
[12, 13]
(TDO)
(TM S)
(TCK )
(TDI)
1
Description
t TM SS
t TDIS
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
Figure 3. TAP Timing
2
t TM SH
t TDIH
t TH
DON’T CA RE
R
/t
F
= 1 ns.
t
TL
3
t CY C
UNDEFINED
4
t TDOX
t TDOV
5
Min
50
20
20
–
–
0
5
5
5
5
5
5
6
Max
20
–
–
–
5
–
–
–
–
–
–
–
Page 19 of 35
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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