CY7C1471BV33_11 CYPRESS [Cypress Semiconductor], CY7C1471BV33_11 Datasheet - Page 11

• Manufacturer Part Number: CY7C1471BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP
On the next clock rise the data presented to DQs and DQP
a subset for Byte Write operations, see section
Read/Write on page 13
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BW
signals. The CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 provide Byte Write capability that is described
in the section
WE with the selected BW
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte write capability is
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
Because the CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are common I/O devices, do not drive data into
the device when the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQs and
DQP
precaution, DQs and DQP
the data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in section
Accesses on page
ZZ Mode Electrical Characteristics
Document Number: 001-15029 Rev. *E
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
X
inputs. Doing so tri-states the output drivers. As a safety
3
are all asserted active, and (3) WE is asserted LOW.
Truth Table for Read/Write on page
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
11. When ADV/LD is driven HIGH on the
for details), input is latched into the
X
X
input selectively writes to only the
are automatically tri-stated during
Description
Truth Table for
Single Write
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
13. The input
X
.
1
, CE
X
(or
2
X
,
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
subsequent clock rise, the chip enables (CE
and WE inputs are ignored and the burst counter is incremented.
Drive the correct BW
write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
CE
t
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table
(MODE = GND)
ZZREC
Test Conditions
DD
DD
1
Address
Address
A1: A0
A1: A0
, CE
– 0.2 V
– 0.2 V
First
First
00
01
10
00
01
10
11
11
after the ZZ input returns LOW.
2
, and CE
3
Address
Address
Second
Second
, must remain inactive for the duration of
A1: A0
A1: A0
X
01
00
11
10
01
10
11
00
inputs in each cycle of the burst write to
DD
)
2t
Min
CYC
–
–
–
0
Address
Address
A1: A0
A1: A0
Third
Third
10
00
01
10
00
01
11
11
2t
2t
Max
120
1
CYC
CYC
–
, CE
–
Address
Address
2
Page 11 of 35
Fourth
A1: A0
Fourth
A1: A0
, and CE
11
10
01
00
11
00
01
10
Unit
mA
ns
ns
ns
ns
3
)
[+] Feedback