CY7C1471BV33_11 CYPRESS [Cypress Semiconductor], CY7C1471BV33_11 Datasheet - Page 25

• Manufacturer Part Number: CY7C1471BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5 V when V
1.25 V when V
Notes
Document Number: 001-15029 Rev. *E
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
18. This part has an internal voltage regulator; t
19. t
20. At any supplied voltage and temperature, t
21. This parameter is sampled and not 100% tested.
Parameter
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
from steady-state voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
CHZ
, t
CLZ
[18]
,t
OELZ
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low-Z
Clock to high-Z
OE LOW to output valid
OE LOW to output low-Z
OE HIGH to output high-Z
Address setup before CLK rise
ADV/LD setup before CLK rise
WE, BW
CEN setup before CLK rise
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BW
CEN hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
DDQ
, and t
= 2.5 V. Test conditions shown in (a) of
OEHZ
X
X
setup before CLK rise
hold after CLK rise
are specified with AC test conditions shown in part (b) of
[19, 20, 21]
[19, 20, 21]
POWER
OEHZ
Description
[19, 20, 21]
[19, 20, 21]
is less than t
is the time that the power must be supplied above V
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
OELZ
and t
AC Test Loads and Waveforms on page 24
CHZ
is less than t
AC Test Loads and Waveforms on page
CLZ
to eliminate bus contention between SRAMs when sharing the same
DD
Min
7.5
2.5
2.5
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
(minimum) initially, before a read or write operation is initiated.
133 MHz
Max
6.5
3.8
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
24. Transition is measured ±200 mV
unless otherwise noted.
Min
3.0
3.0
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
–
–
–
0
–
117 MHz
DDQ
= 3.3 V and is
Max
8.5
4.5
3.8
4.0
Page 25 of 35
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Unit
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