CY7C1471BV33_11 CYPRESS [Cypress Semiconductor], CY7C1471BV33_11 Datasheet
CY7C1471BV33_11
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CY7C1471BV33_11 Summary of contents
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Features ■ No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133 MHz bus operations with zero wait states ■ Data is transferred on every clock ■ Pin compatible and functionally equivalent ...
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Logic Block Diagram – CY7C1471BV33 (2 M × 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN WRITE ADDRESS ADV/ READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL ...
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Logic Block Diagram – CY7C1475BV33 (1 M × 72) ADDRESS A0, A1, A REGISTER 0 MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ AND DATA COHERENCY ...
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Contents Pin Configuration ............................................................. 5 Pin Definitions .................................................................. 9 Functional Overview ...................................................... 10 Single Read Accesses .............................................. 10 Burst Read Accesses ................................................ 10 Single Write Accesses ............................................... 11 Burst Write Accesses ................................................ 11 Sleep Mode ............................................................... 11 Interleaved Burst Address ...
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Pin Configuration Figure 1. 100-pin TQFP Pinout – CY7C1471BV33 (2 M × 36) DQP DDQ BYTE ...
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Pin Configuration (continued) Figure 2. 100-pin TQFP Pinout – CY7C1473BV33 (4 M × 18 DDQ ...
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Pin Configuration (continued) 165-ball FBGA (15 × 17 × 1.4 mm) Pinout NC/576M NC/1G CE2 A C DQP DDQ DDQ ...
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Pin Configuration (continued) 209-ball FBGA (14 × 22 × 1.76 mm) Pinout DQg DQg A B DQg DQg BWS C DQg DQg BWS D DQg DQg V E DQPg DQPc V DDQ F DQc DQc V ...
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Pin Definitions Name I Input- Address inputs used to select one of the address locations. Sampled at the rising edge Synchronous the CLK Input- Byte write inputs, ...
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Pin Definitions (continued) Name I/O TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG output feature is not used, this pin must be left unconnected. This pin is not ...
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Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE and CE are all asserted active, and ( asserted LOW. 3 The address presented to ...
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Truth Table The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows. Address Operation Used Deselect cycle None Deselect cycle None Deselect cycle None Continue deselect cycle None Read cycle External (begin burst) Read cycle Next (continue burst) NOP/Dummy read External ...
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Truth Table for Read/Write The read/write truth table for CY7C1471BV33 follows. Function Read Write – No bytes written Write byte A – (DQ and DQP ) A A Write byte B – (DQ and DQP ) B B Write byte ...
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IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full ...
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TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Codes” on page 20. Three of these instructions are listed as RESERVED and must not be used. The other five instructions ...
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TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 RUN-TEST/ 0 IDLE Document Number: 001-15029 Rev. *E CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 1 SELECT DR-SCA CAPTURE-DR 0 SHIFT- EXIT1-DR 0 PAUSE- EXIT2-DR 1 ...
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TAP Controller Block Diagram Selection TDI Circuitry TCK TM S Document Number: 001-15029 Rev. *E CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 0 Bypass Register Selection Instruction Register Circuitry Identification Register x ...
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TAP AC Test Conditions Input pulse levels................................................V Input rise and fall times....................................................1 ns Input timing reference levels.......................................... 1.5 V Output reference levels ................................................. 1.5 V Test load termination supply voltage ............................. 1.5 V 3.3-V TAP AC Output Load Equivalent ...
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TAP AC Switching Characteristics [12, 13] Over the Operating Range Parameter Clock t TCK clock cycle time TCYC t TCK clock frequency TF t TCK clock HIGH time TH t TCK clock LOW time TL Output Times t TCK clock ...
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Identification Register Definitions CY7C1471BV33 Instruction Field Revision number (31:29) [14] Device depth (28:24) Architecture/memory type(23:18) Bus width/density(17:12) Cypress JEDEC ID code (11:1) 00000110100 ID register presence indicator (0) Scan Register Sizes Register Name Instruction Bypass ID Boundary scan order – ...
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Boundary Scan Exit Order (2 M × 36) Bit # 165-Ball ID Bit # ...
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Boundary Scan Exit Order (1 M × 72) Bit # 209-Ball ID Bit # ...
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Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied . –55 °C to +125 °C Supply voltage on ...
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Electrical Characteristics [15, 16] Over the Operating Range (continued) Parameter Description I Automatic CE SB4 power-down current—TTL inputs Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description C Address input capacitance ADDRESS ...
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Switching Characteristics Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5 V when V 1.25 V when V = 2.5 V. Test conditions shown in (a) of DDQ Parameter Description [18] t POWER ...
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Switching Waveforms Figure 5 shows read-write timing waveform CYC CLK t CENS t CENH CEN t CES t CEH CE ADV/ ADDRESS ...
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Switching Waveforms (continued) Figure 6 shows NOP, STALL and DESELECT Cycles waveform. Figure 6. NOP, STALL, and DESELECT Cycles 1 2 CLK CEN CE ADV/ [A: ADDRESS D(A1) DQ COMMAND WRITE READ D(A1) Q(A2) Notes 25. ...
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Switching Waveforms (continued) Figure 7 shows ZZ Mode timing waveform. CLK ZZI I SUPPLY I DDZZ ALL INPUTS (except ZZ) Outputs (Q) Notes 28. Device must be deselected when entering ZZ mode. See the 29. DQs ...
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Ordering Information Table 1 lists the CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. ...
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Package Diagrams Document Number: 001-15029 Rev. *E CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) 51-85050 *D Page [+] Feedback ...
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Package Diagrams (continued) Document Number: 001-15029 Rev. *E CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm) 51-85165 *C Page [+] Feedback ...
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Package Diagrams (continued) Document Number: 001-15029 Rev. *E CY7C1471BV33, CY7C1473BV33, CY7C1475BV33 Figure 10. 209-ball FBGA (14 × 22 × 1.76 mm) 51-85167 *A Page [+] Feedback ...
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Reference Information Acronyms Table 2. Acronyms Acronym Description FBGA fine-pitch ball grid array I/O input/output JTAG joint test action group LSB least significant bit MSB most significant bit PLL phase-locked loop SRAM static random access memory TAP test access port ...
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Document History Page Document Title: CY7C1471BV33/CY7C1473BV33/CY7C1475BV33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 001-15029 Orig. of Submission Revision ECN Change ** 1024500 VKN/KKVT MP *A 1274731 VKN/AESA *B 2183566 ...
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