CY7C1471BV33_11 CYPRESS [Cypress Semiconductor], CY7C1471BV33_11 Datasheet - Page 26

• Manufacturer Part Number: CY7C1471BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 5
Notes
Document Number: 001-15029 Rev. *E
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE
24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
COM M AND
ADDRESS
ADV/LD
BW
shows read-write timing waveform.
CEN
CLK
W E
DQ
OE
CE
X
t CENS
t CES
t AS
W RITE
D(A1)
A1
1
1
is LOW, CE
t CENH
t CEH
t AH
t DS
W RITE
D(A1)
D(A2)
A2
2
2
t CH
is HIGH, and CE
t DH
t CYC
t CL
D(A2+1)
D(A2)
BURST
W RITE
3
[22, 23, 24]
3
is LOW. When CE is HIGH, CE
Figure 5. Read/Write Timing
CY7C1471BV33, CY7C1473BV33, CY7C1475BV33
DON’T CARE
D(A2+1)
READ
Q(A3)
A3
4
t CDV
t CLZ
Q(A4)
READ
Q(A3)
A4
5
t DOH
t OEHZ
UNDEFINED
1
is HIGH, CE
Q(A4+1)
BURST
Q(A4)
READ
6
t OEV
t OELZ
2
is LOW or CE
Q(A4+1)
W RITE
D(A5)
A5
7
t CHZ
t DOH
3
is HIGH.
READ
Q(A6)
A6
D(A5)
8
W RITE
D(A7)
Q(A6)
A7
9
DESELECT
Page 26 of 35
D(A7)
10
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