DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 51

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Byte Peripheral Interface Configuration Timing
X-Ref Target - Figure 14
Table 55: Timing for Byte-wide Peripheral Interface Configuration Mode
DS705 (v1.1) January 20, 2009
Product Specification
T
T
T
T
T
T
T
T
(Open-Drain)
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
Symbol
PROG_B
LDC[2:0]
PUDC_B
CSO_B
A[25:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
R
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
T
MINIT
Figure 14: Waveforms for Byte-wide Peripheral Interface Configuration
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Byte 0
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
T
INITADDR
000_0001
Byte 1
T
AVQV
Data
Minimum
New ConfigRate active
T
50
CCLK1
Address
0
0
5
T
See T
CCO
Data
See
See
See
SMDCC
T
T
DCC
CCLKn
Maximum
Address
Table 47
Table 47
Table 51
in
5
-
-
-
Table 52
Data
DS705_15_061908
Address
T
cycles
Units
CCLK1
T
ns
ns
ns
Data
CCD
51