DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 27

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions.
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of V
High logic level of V
Some standards also require the application of a bias
voltage to the V
input-switching threshold. The measurement point of the
Input signal (V
and V
The Output test setup is shown in
voltage V
end of which is connected to the Output. For each standard,
R
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
Table 27: Test Methods for Timing Measurement at I/Os
DS705 (v1.1) January 20, 2009
Product Specification
Single-Ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
T
and V
Signal Standard
H
(IOSTANDARD)
.
T
T
is applied to the termination resistor R
generally take on the standard values
Table 27
R
Rising
Falling
M
REF
) is commonly located halfway between V
H
pins of a given bank to properly set the
lists the conditions to use for each
is applied to the Input under test.
V
REF
0.75
1.25
1.25
0.9
0.9
0.9
1.1
0.9
0.9
1.5
1.5
-
-
-
-
-
-
-
Figure
(V)
8. A termination
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Note 3
V
Inputs
L
T
0
0
0
0
0
0
– 0.75
– 0.75
– 0.75
– 0.75
L
, the other
(V)
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
and a
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L
V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
REF
REF
REF
REF
REF
REF
REF
Note 3
V
LVCMOS, LVTTL), then R
open connection, and V
measurement point (V
used at the Output.
X-Ref Target - Figure 8
H
3.3
3.3
2.5
1.8
1.5
1.2
+ 0.75
+ 0.75
+ 0.75
+ 0.75
(V)
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
Notes:
1.
FPGA Output
The names shown in parentheses are
used in the IBIS file.
Figure 8: Output Test Setup
R
T
1M
1M
1M
1M
1M
1M
25
25
50
50
50
25
50
50
25
50
25
50
25
(Ω)
M
Outputs
T
) that was used at the Input is also
is set to zero. The same
T
V
is set to 1 MΩ to indicate an
T
(V
R
REF
C
V
0.75
1.25
1.25
T
T
3.3
1.5
0.9
0.9
1.8
0.9
0.9
1.5
1.5
L
0
0
0
0
0
0
0
(R
(V)
(C
)
V
M
REF
DS705_09_061908
REF
(V
)
MEAS
)
)
Inputs and
Outputs
V
V
V
V
V
V
V
V
V
V
V
V
1.65
1.25
0.75
0.94
2.03
M
1.4
0.9
0.6
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
(V)
27