DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 48

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Slave Parallel Mode Timing
X-Ref Target - Figure 12
Table 52: Timing for the Slave Parallel Configuration Mode
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
Notes:
1.
2.
(Open-Drain)
Setup Times
T
T
T
Hold Times
T
T
T
Clock Timing
T
T
F
SMDCC
SMCSCC
SMCCW
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
RDWR_B
PROG_B
Symbol
The numbers in this table are based on the operating conditions set forth in
Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
To pause configuration, pause CCLK instead of deasserting CSI_B. See the section in Chapter 7 called “Non-Continuous SelectMAP Data
Loading” in
D0 - D7
(Inputs)
INIT_B
(Input)
CSI_B
(Input)
(Input)
(Input)
CCLK
(2)
R
UG332
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal
at the CCLK input pin
for more details.
Figure 12: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
No bitstream compression
With bitstream compression
Description
Byte 0
T
SMCSCC
www.xilinx.com
T
SMCCD
Byte 1
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table
8.
T
T
SCCH
MCCH
1/F
CCPAR
Byte n
Min
17
7
7
1
0
0
5
5
0
0
T
T
MCCL
SCCL
T
SMCCCS
Byte n+1
Max
80
80
-
-
-
-
-
-
-
-
DS705_13_061908
T
SMWCC
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
48