DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 31

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 29: Recommended Number of Simultaneously
Switching Outputs per V
DS705 (v1.1) January 20, 2009
Product Specification
LVCMOS15
LVCMOS12
PCI33_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
Signal Standard
(IOSTANDARD)
R
QuietIO
QuietIO
Slow
Slow
Fast
Fast
CCO
12
12
12
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
2
4
6
2
4
6
-GND Pair (V
Top, Bottom
(Banks 0,2)
CSG484, FGG676
55
31
18
25
10
70
40
31
40
31
55
16
17
10
18
–
–
6
–
–
–
–
–
–
–
–
–
–
–
–
–
7
–
–
8
6
Package Type
CCAUX
Left, Right
(Banks 1,3)
=3.3V)
55
31
18
15
10
25
10
70
40
31
31
20
40
25
18
31
13
55
36
36
16
20
17
15
18
10
6
4
3
9
8
5
8
9
9
7
www.xilinx.com
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table 29: Recommended Number of Simultaneously
Switching Outputs per V
Notes:
1.
2.
3.
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331, Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board layout practice. This table assumes the following
parasitic factors: combined PCB trace and land inductance per
V
Test limits are the V
standard.
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689, Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
CCO
Signal Standard
(IOSTANDARD)
and GND pin of 1.0 nH, receiver capacitive load of 15 pF.
IL
/V
IH
CCO
voltage limits for the respective I/O
-GND Pair (V
Top, Bottom
(Banks 0,2)
CSG484, FGG676
22
27
22
27
22
27
27
22
27
4
8
–
5
–
–
3
–
9
–
4
3
Package Type
Inputs Only
Inputs Only
CCAUX
Left, Right
(Banks 1,3)
=3.3V)
10
–
–
4
–
–
–
–
–
–
–
8
2
4
4
7
1
9
4
5
3
31