DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 32

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Configurable Logic Block Timing
Table 30: CLB (SLICEM) Timing
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
Propagation Times
T
Set/Reset Pulse Width
T
AS
AH
CKO
DICK
CKDI
CH
CL
TOG
ILO
RPW_CLB
The numbers in this table are based on the operating conditions set forth in
Symbol
R
When reading from the FFX (FFY) Flip-Flop, the time from the active
transition at the CLK input to data appearing at the XQ (YQ) output
Time from the setup of data at the F or G input to the active transition at the
CLK input of the CLB
Time from the setup of data at the BX or BY input to the active transition at
the CLK input of the CLB
Time from the active transition at the CLK input to the point where data is last
held at the F or G input
Time from the active transition at the CLK input to the point where data is last
held at the BX or BY input
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
The time it takes for data to travel from the CLB’s F (G) input to the X (Y)
output
The minimum allowable pulse width, High or Low, to the CLB’s SR input
Description
www.xilinx.com
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table
8.
0.75
0.36
1.88
0.00
0.00
0.75
1.61
Min
Speed Grade
–
0
–
-4
Max
0.68
0.71
667
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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