DS705 XILINX [Xilinx, Inc], DS705 Datasheet - Page 38

• Manufacturer Part Number: DS705
• Description: XA Spartan-3A DSP Automotive FPGA Family Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Digital Clock Manager Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 39
ones in the DLL tables. DLL specifications that do not
Delay-Locked Loop
Table 37: Recommended Operating Conditions for the DLL
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
3.
4.
5.
Input Frequency Ranges
F
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
CLKFB_DELAY_VAR_EXT
CLKIN
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
through
CLKIN_FREQ_DLL
(Table 37
R
Symbol
Table
and
42) supersede any corresponding
Table
38) apply to any application
Allowable variation of off-chip feedback delay from the DCM output to
Frequency of the CLKIN clock input
CLKIN pulse width as a percentage of the
CLKIN period
Cycle-to-cycle jitter at the CLKIN input
Period jitter at the CLKIN input
the CLKFB input
(4)
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Description
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
change with the addition of DFS or PS functions are
presented in
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
F
F
F
F
Table 37
CLKIN
CLKIN
CLKIN
CLKIN
< 150 MHz
> 150 MHz
< 150 MHz
> 150 MHz
Table
and
Table
39.
38.
40%
45%
Speed Grade
Min
5
(2)
-
-
-
-
-4
250
±300
±150
Max
60%
55%
±1
±1
(3)
Units
MHz
ps
ps
ns
ns
-
-
38