ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 167

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
Table 74.
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
2. Formula for SSC Clock Cycle time: t
3. Partially tested, guaranteed by design characterization.
t
t
t
t
Symbol
307p
308p
307
308
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only with CPU clock equal to (or lower than) 32 MHz.
baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t
SR
SR
SR
SR
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
SSC master mode timings (continued)
Figure 61. SSC master timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
2. The bit timing is repeated for all bits to be transmitted or received.
SCLK
MTSR
MRST
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
Parameter
(1)
t
305
300
t
1st in bit
307
= 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
1st out bit
t
300
t
308
t
305
t
301
t
(<SSCBR> = 0002h)
Maximum baudrate
37.5
304
Min
50
25
@ f
0
2nd out bit
6.6 Mbaud
CPU
2nd In bit
t
302
= 40 MHz
t
303
(1)
Max
t
306
–
–
–
–
300
(2)
is 125ns (corresponding to 8Mbaud).
(<SSCBR> = 0001h - FFFFh)
2TCL + 12.5
4TCL
2TCL
t
305
Min
Variable baudrate
0
Last in bit
t
Electrical characteristics
307
Last out bit
t
308
Max
–
–
–
–
167/176
Unit
ns
ns
ns
ns