ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 158

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
Table 71.
1. RW-delay and t
2. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
3. Partially tested, guaranteed by design characterization.
158/176
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
39
41
82
83
46
47
48
49
50
51
53
68
55
57
changes before the end of RD have no impact on read cycles.
SR
CC
CC
CC
SR
SR
CC
CC
CC Data valid to WrCS
SR Data hold after RdCS
SR
SR
CC
CC Data hold after WrCS
Latched CS low to Valid Data
In
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS
(with RW-delay)
Address setup to RdCS,
WrCS
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Demultiplexed bus timings (continued)
A
refer to the next following bus cycle.
Parameter
(3)
(3)
15.5 + t
14 + 2t
-8.5 + t
28 + t
10 + t
2 + 2t
2 + t
2 + t
Min
–
–
–
0
–
–
f
TCL = 12.5ns
CPU
F
F
C
C
A
A
F
C
= 40 MHz
+ t
16.5 + t
16.5 + t
16.5 +
4 + t
4 + t
Max
C
–
–
–
–
–
–
–
–
–
+ 2t
C
F
C
F
A
TCL - 10.5 + 2t
2TCL - 11 + 2t
TCL - 10.5 + t
2TCL - 9.5 + t
3TCL - 9.5 + t
TCL - 10.5 + t
2TCL - 15 + t
-8.5 + t
1/2 TCL = 1 to 40 MHz
Min
Variable CPU clock
–
–
–
0
–
–
F
C
F
C
C
F
A
A
2TCL - 8.5 + t
2TCL - 21 + t
3TCL - 21 + t
TCL - 8.5 + t
3TCL - 21 +
+ t
Max
C
–
–
–
–
–
–
–
–
–
+ 2t
ST10F272M
A
F
C
C
F
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns