ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 144

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
24.8.7
24.8.8
Table 62.
144/176
1
1
1
1
0
(P0H.7-5)
P0.15-13
1
1
0
0
1
1
0
1
0
1
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.
Phase Locked Loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (f
f
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f
locked to f
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
keep it locked on f
one TCL period.
This is especially important for bus cycles using wait states and for example, such as for the
operation of timers or serial interfaces. For all slower operations and longer periods (for
example, pulse train generation or measurement, or lower baudrates) the deviation caused
by the PLL jitter is negligible. Refer to next
Voltage controlled oscillator
The ST10F272M implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following
table gives a detailed summary of the internal settings and VCO frequency.
Internal PLL divider mechanism
XTAL
5.3 to 10.6 MHz
XTAL frequency
6.4 to 8 MHz
1 to 40 MHz
4 to 8 MHz
4 to 8 MHz
x F). With every F’th transition of f
XTAL
(1)
. The slight variation causes a jitter of f
(1)
XTAL
prescaler
f
f
f
f
XTAL
XTAL
XTAL
XTAL
. The relative deviation of TCL is the maximum when it is referred to
Input
–
/ 4
/ 4
/ 4
/ 4
Multiply by
64
48
64
40
PLL bypassed
XTAL
Section 24.8.9: PLL jitter
PLL
the PLL circuit synchronizes the CPU clock to
Divide by
Table
4
4
2
2
CPU
61). The PLL multiplies the input
which also effects the duration of
CPU
prescaler
Output
is constantly adjusted so it is
–
–
–
–
–
for more details.
CPU frequency
f
CPU
f
f
f
f
f
XTAL
XTAL
XTAL
XTAL
XTAL
ST10F272M
= f
XTAL
CPU
CPU
x 4
x 3
x 8
x 5
x 1
to
x F
=