ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 165
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ST10F272M-4Q3
Manufacturer Part Number
ST10F272M-4Q3
Description
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST10F272M-4Q3.pdf
(175 pages)
- Current page: 165 of 175
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ST10F272M
24.8.19
External bus arbitration
V
Table 73.
1. Partially tested, guaranteed by design characterization
Figure 59. External bus arbitration (releasing the bus)
1. The ST10F272M will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t
t
t
t
t
t
t
t
Symbol
61
62
63
64
65
66
67
DD
= 5V ± 10%, V
SR
CC
CC
CC CSx release
CC CSx drive
CC Other signals release
CC Other signals drive
CLKOUT
HOLD
HLDA
BREQ
CSx
(P6.x)
Others
HOLD input setup time
to CLKOUT
CLKOUT to HLDA high
or BREQ low delay
CLKOUT to HLDA low
or BREQ high delay
External bus arbitration timings
Parameter
SS
(1)
= 0V, T
t
61
A
(1)
= -40 to +125°C, C
1)
1)
18.5
Min
-4
-4
f
–
–
–
–
TCL = 12.5ns
CPU
64
= 40 MHz
.
L
t
66
t
= 50pF
63
Max
12.5
12.5
20
15
20
15
–
t
t
62
64
3)
1/2 TCL = 1 to 40 MHz
2)
Variable CPU clock
18.5
Min
-4
-4
–
–
–
–
Electrical characteristics
Max
12.5
12.5
20
15
20
15
–
165/176
Unit
ns
ns
ns
ns
ns
ns
ns
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