ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 128

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
Table 56.
1. Not 100% tested, guaranteed by design characterization.
2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
3. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,
4. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
5. Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the
6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
7. The maximum current may be drawn while the respective signal line remains inactive.
8. The minimum current must be drawn in order to drive the respective signal line active.
9. The power supply current is a function of the operating frequency (f
10. The power supply current is a function of the operating frequency (f
11. The Idle mode supply current is a function of the operating frequency (f
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0V to 0.1V or at V
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Stand-by supply current
(RTC on, 32 kHz Oscillator on,
main V
Stand-by supply current
(V
DD
and the voltage is imposed by the external circuitry.
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next
circuitry.
specified range (that is, V
not exceed 50mA. The supply voltage must remain within the specified limits.
for CS output and the open drain function is not enabled.
illustrated in
disconnected and all inputs at V
doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in
disconnected and all inputs at V
doing the following:
- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in
all inputs at V
- 0.1V to V
Regulator is assumed to be off; if it is not, an additional 1mA must be added.
transient condition)
DD
off, V
DD
DC characteristics (continued)
Figure 38
Figure 38
Figure 37
, V
IL
Parameter
STBY
or V
AREF
IH
on)
= 0V, all outputs (including pins configured as outputs) disconnected. Also, the Main Voltage
, RSTIN pin at V
below. This parameter is tested at V
below. This parameter is tested at V
below. These parameters are tested and at maximum CPU clock with all outputs disconnected and
(12)
(1)(12)
OV
> V
DD
IL
IL
or V
or V
+ 0.3V or V
IH1min
IH
IH
, RSTIN pin at V
, RSTIN pin at V
.
I
I
SB2
SB3
OV
Symbol
< -0.3V). The absolute sum of input overload currents on all port pins may
IH1min
IH1min
DDmax
DDmax
: this implies I/O current is not considered. The device is
: this implies I/O current is not considered. The device is
Min
and at maximum CPU clock frequency with all outputs
and at maximum CPU clock frequency with all outputs
–
–
–
Limit values
CPU
CPU
CPU
is expressed in MHz). This dependency is
is expressed in MHz). This dependency is
is expressed in MHz). This dependency is
Max
120
500
Figure 37
2.5
for a scheme of the input
Unit
mA
µA
µA
T
Test condition
T
A
V
V
A
STBY
STBY
= T
= T
ST10F272M
J
J
–
= 5.5V
= 5.5V
= 125°C
= 25°C
DD