ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 141

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
24.8
24.8.1
24.8.2
AC characteristics
Test waveforms
Figure 43. Input / output waveforms
Figure 44. Float waveforms
Definition of internal timing
The internal operation of the ST10F272M is controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (for example, pipeline) or external (for example,
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate f
This influence must be regarded when calculating the timings for the ST10F272M.
The example for PLL operation shown in
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
For timing purposes a port pin is no longer floating when V
It begins to float when a 100mV change from the loaded V
V
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at V
LOAD
0.4V
CPU
2.4V
V
V
LOAD
LOAD
.
+ 0.1V
- 0.1V
2.0V
0.8V
Figure 45
IH
Test Points
min. for a logic ‘1’ and V
Reference
Timing
Points
V
V
OL
OH
refers to a PLL factor of 4.
OH
LOAD
0.8V
2.0V
/V
OL
changes of ±100mV.
level occurs (I
Electrical characteristics
IL
max for a logic ‘0’.
V
V
OL
OH
OH
+ 0.1V
/I
- 0.1V
OL
= 20mA).
CPU
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. Both