ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 139
ST10F272M-4Q3
Manufacturer Part Number
ST10F272M-4Q3
Description
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST10F272M-4Q3.pdf
(175 pages)
- Current page: 139 of 175
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ST10F272M
The considerations above lead to impose new constraints to the external circuit, to reduce
the accuracy error due to the voltage drop on C
above, it is simple to derive the following relation between the ideal and real sampled
voltage on C
From this formula, in the worst case (when V
assuming to accept a maximum error of half a count (~2.44mV), a constraint is immediately
evident on C
In the next section an example of how to design the external network is provided, assuming
some reasonable values for the internal parameters and making a hypothesis on the
characteristics of the analog signal to be sampled.
Example of external network sizing
The following hypotheses are formulated in order to proceed in designing the external
network on A/D Converter input pins:
●
●
●
●
●
●
●
●
●
●
●
Analog Signal Source Bandwidth (f
conversion Rate (f
Sampling Time (T
Pin Input Capacitance (C
Pin Input Routing Capacitance (C
Sampling Capacitance (C
Maximum Input Current Injection (I
Maximum Analog Source Voltage (V
Analog Source Impedance (R
Channel Switch Resistance (R
Sampling Switch Resistance (R
S
F
:
value:
S
C
): 1µs
): 25 kHz
P1
S
-----------
V A2
): 4pF
): 5pF
V A
S
SW
): 100Ω
AD
=
): 500Ω
P2
------------------------------------------------------------
C P1
): 200Ω
C F 2048 C S
INJ
0
): 1pF
): 10 kHz
AM)
C P1
): 3mA
>
+
: 12V
A
C P2
+
is maximum, that is for instance 5V),
S
C P2
; from the two charge balance equations
⋅
+
C F
+
C F
+
C S
Electrical characteristics
139/176
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