ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 164

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ST10F272M-4Q3

Manufacturer Part Number
ST10F272M-4Q3
Description
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Electrical characteristics
164/176
Figure 58. CLKOUT and READY
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
7. The next external bus cycle may start here.
LOW at this sampling point terminates the currently running bus cycle.
WR).
CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t
synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4).
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
without MTTC wait state this delay is zero.
CLKOUT
ALE
RD, WR
Synchronous
READY
Asynchronous
READY
t
t
58
32
3)
t
t
t
59
30
34
Running cycle 1)
2)
t
t
33
31
t
t
35
58
3)
t
37
3)
t
t
36
59
t
5)
29
t
35
wait state
READY
3)
t
36
37
in order to be safely
MUX / Tri-state 6)
t
60
4)
6)
7)
ST10F272M

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