mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 87

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.2.3.3.31
Address 0xAE
Reset
This register defines the period length of the bus guardian tick to be provided by the CC to the bus guardian.
The value BGT[0:4], is expressed in multiples of the CC microtick. Writing this register is possible only
during the configuration state. The value of this register must be within the range [2:16].
3.2.3.3.32
Address 0x3C
Reset
This register specifies the configurable part of the delay between the reset of the CONFIG bit (host writing
MCR0.CONFIG) and the point in time when the controller actually leaves the configuration state (see
Section 3.9.2, “Configuration
The host may write this register only during the configuration state.
Freescale Semiconductor
Reserved
Reserved
DC15
DC7
rw*
rw*
15
15
7
7
r
r
undefined state
0x0
Bus Guardian Tick Register (BGTR)
Delay Counter Register (DCR)
The SYNCHR value overwrites the header CRC field of a transmit message
buffer that: a) has the same frame ID as the SYNCF[0:10] field of the
SYNCFR (see
b) was selected by the CC for transmission as a sync message.
Reserved
Reserved
DC14
DC6
rw*
rw*
14
14
6
6
r
r
the configured value * 8 = delay in microticks
Reserved
Reserved
Section 3.2.3.3.29, “Sync Frame Register
State”). The delay is configurable in steps of eight microticks, i.e.
DC13
DC5
rw*
rw*
13
13
5
5
r
r
Figure 3-44. Bus Guardian Tick Register
Figure 3-45. Delay Counter Register
MFR4200 Data Sheet, Rev. 0
Reserved
BGT4
DC12
DC4
rw*
rw*
rw*
12
12
4
4
r
NOTE
Reserved
BGT3
DC11
DC3
rw*
rw*
rw*
11
11
3
3
r
Reserved
BGT2
DC10
DC2
(SYNCFR)”), and
rw*
rw*
rw*
10
10
2
2
r
Reserved
Memory Map and Registers
BGT1
DC9
DC1
rw*
rw*
rw*
9
1
9
1
r
Reserved
BGT0
Eqn. 3-6
DC8
DC0
rw*
rw*
rw*
8
0
8
0
r
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