mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 153

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.4.1.2
The IFLG flag is provided by the CC. It performs different functions depending on the configuration of the
corresponding message buffer.
Receive message buffer:
The flag indicates that the controller has updated the receive message buffer due to frame reception (update
of data fields and the slot status vector after reception of a valid frame, or update of the slot status vector
after reception of an invalid frame). The host can clear the flag by a buffer lock operation.
1 – The controller sets the flag when the receive message buffer was updated after a frame reception. The
host must process received data and clear the IFLG bit.
0 – The message buffer is not updated, or the host has cleared the IFLG bit implicitly by locking the
message buffer.
Transmit message buffer:
The flag indicates that the message buffer is empty, or that the controller has transmitted a frame from that
message buffer. The host can clear the flag by a buffer lock operation.
1 – The flag is set by the controller when the transmit message buffer is empty/not updated (i.e. has been
transmitted). The host may write new data to the buffer.
0 – The flag is cleared implicitly by the host when the transmit message buffer is updated (i.e. locked).
Receive FIFO buffer:
The flag has no meaning; it will never be set.
3.4.1.3
This bit enables the corresponding message buffer as an IFLG bit interrupt source. If the message buffer
is configured as a receive message buffer, the generated by the CC interrupt is a read interrupt. If the
message buffer is configured as a transmit message buffer, the interrupt generated by the CC is a write
interrupt.
1 – The corresponding message buffer interrupt is enabled.
Freescale Semiconductor
1. The IFLG bit is set to the value of the CFG bit with each write to a BUFCSnR register, during the
2. If the host does not write to a BUFCSnR register during the configuration state, the IFLG holds
configuration state. During normal operation, the controller updates the IFLG bit after frame
transmission (transmit message buffer) and after frame reception (receive message buffer).
— If CFG is clear (receive message buffer) the CC clears the IFLG bit, also, indicating that the
— If CFG is set (transmit message buffer) the CC sets the IFLG bit, also, indicating that the
the value it had before it entered the configuration state.
receive message buffer does not hold new receive data.
transmit message buffer is empty and will be filled by the host application.
IFLG — Interrupt Status Flag
IENA — IFLG Interrupt Enable
MFR4200 Data Sheet, Rev. 0
Message Buffer Control, Configuration, Status and Filtering Register Set
NOTE
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