mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 120

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mfr4200

Manufacturer Part Number
mfr4200
Description
Flexray Communication Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MFR4200 FlexRay Communication Controller
3.2.3.6.9
Address OSFID0R=0x3E0 … OSFID15R=0x3FE
Reset
These registers hold the frame IDs of all sync frames received in odd communication cycles and used for
clock synchronization. The CC does not change the odd ID values from the end of the static part in the odd
cycle to the beginning of the NIT in the even communication cycle.
120
Reserved
ID7
15
rh
7
r
undefined state
Selection Register
Odd Sync Frame ID n Register, n = [0:15] (OSFIDnR)
If a CC is configured to send sync frames (see
Frame Register
OSFID0R.
Slot Status
Reserved
SSS0R
SSS1R
SSS2R
SSS3R
ID6
14
Empty slots exhibit the slot status 0x00 for both channels, because the
slot status registers SSnR do not include the slot status channel bit.
rh
6
r
Figure 3-81. Odd Sync Frame ID n Register, n = [0:15]
Reserved
Table 3-8. Mapping between SSSnR and SSnR
(SYNCFR)”), the CC will store its sync frame ID in register
ID5
13
rh
5
r
Channel A
(low byte)
Even communication cycle
SS0R
SS2R
SS4R
SS6R
MFR4200 Data Sheet, Rev. 0
Reserved
ID4
12
rh
4
r
NOTE
(high byte)
Channel B
SS0R
SS2R
SS4R
SS6R
Reserved
ID3
11
rh
3
r
Section 3.2.3.3.29, “Sync
Channel A
(low byte)
Odd communication cycle
ID10
SS1R
SS3R
SS5R
SS7R
ID2
10
rh
rh
2
Freescale Semiconductor
ID9
ID1
(high byte)
Channel B
rh
rh
9
1
SS1R
SS3R
SS5R
SS7R
ID8
ID0
rh
rh
8
0

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