mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 174

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
place every time the communication controller receives a semantically valid and syntactically correct
frame.
An example of operations during a frame reception is shown on the
3.5.6.1.1
After every successful frame reception, the CC sets the flag IFLG of a matching buffer. This flag indicates
that a frame has been received and stored in a buffer, and the host can read it to empty the buffer for the
next reception. All IFLG bits are logically OR’ed and connected to the host interrupt line. The host receives
an interrupt if at least one IFLG is set and not masked by the appropriate IENA bit in the BUFCSnR
register.
To read a receive message buffer the host must perform the following steps:
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1. Process an interrupt by reading the ISR registers, if necessary. or check the IFLG bits of receive
2. Locate one IFLG interrupt source register by reading the receive message buffer interrupt vector
3. Send a lock request (write LOCK bit with the value ‘1’) for the corresponding message buffer, to
4. Wait for lock acknowledge (LOCK bit reads as value ‘1’).
5. Read the active receive message buffer.
6. Send an unlock request for the message buffer.
message buffers.
register (see
make it accessible through the active receive message buffer.
The Host Operations during Reception
Section 3.2.3.6, “Interrupt and Error Signaling Related Status
MFR4200 Data Sheet, Rev. 0
Figure
3-136.
Registers”).
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