mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 165

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Locking errors:
Refer to
points are as follows.
Locking timing:
If a transmit message buffer (single or double) was committed for transmission in slot n and unlocked by
the host, and if the CC has scheduled this buffer for transmission in slot n, then this buffer is locked by the
CC for transmission (see the BB bit description in
the time shown in
Freescale Semiconductor
•
•
•
•
If the controller receives two frames for a receive message buffer that is locked by the host, the
controller discards the older frame and sets the frame lost error FLE in the CHIER register.
A message buffer committed for transmission (its BUFCMT bit is ‘1’) cannot be locked. If the host
sends a lock request for the committed transmit message buffer, a lock error is raised.
The host cannot access the odd buffers (CC part buffers) of the double transmit message buffers. If
it sends a locking request for any odd buffer of a double transmit message buffer, a lock error is
raised.
If the host tries to lock a second transmit or receive buffer or a second FIFO buffer, the controller
issues a lock error. See the description of the RBLE, TBLE, FBLE bits in
Error Register
Section 3.2.3.6.3, “CHI Error Register
communication cycle
1
If the host issues a lock request here, the CC does not grant the lock request, but sets the BB flag
in the CHIER register indicating a transmit message buffer busy lock error.
The host can write the BUFCMT bit of a message buffer only after the buffer
is locked and available through an active buffer. The BUFCMT bit is part of
the message buffer control, configuration, and status registers
BUFCSnR[0:58] (see
Configuration and Status
Figure
Figure 3-133. Buffer Busy Bit Timing for a Transmit Message Buffer
(CHIER)”.
3-133.
locking possible
Section 3.4.1, “Message Buffer Control,
MFR4200 Data Sheet, Rev. 0
Register”).
TX Buffer Locking (Slot ID = n)
(CHIER)” for a detailed description. The most important
NOTE
Section 3.2.3.6.3, “CHI Error Register
4 µT
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
slot n-1
locking impossible
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
x x x x x x x x x x x x x
slot n
Message Buffer Handling and Operations
1
4 µT
Section 3.2.3.6.3, “CHI
locking possible
(CHIER)”) for
NIT
165