mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 164

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
Locking principles:
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2. The host checks that the message buffer is locked (accessible through an active buffer) by reading
3. At the same time, the host checks for a locking error by reading the lock interrupt flag CHIERRIF
4. In the event of a locking error, the host may determine the cause of the error (see
5. Depending on the message buffer type, the host performs buffer read or read/write operations
6. When the host has finished the message buffer update, it can unlock the message buffer by writing
7. The host can start a locking procedure for another message buffer.
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the LOCK bit. If the resulting value is ‘1’, the message buffer was locked successfully. Otherwise,
the message buffer could not be locked and the lock request must be repeated.
in the interrupt status register ISR0 (see
Section 3.2.3.6.3, “CHI Error Register
when the message buffer becomes available through an active buffer (LOCK = ‘1’). All transmit
message buffers are accessible through the active transmit message buffer, receive message
buffers through the active receive message buffer, and FIFO buffers through the active receive
FIFO buffer. Once the message buffer is locked, the host accesses it without checking the LOCK
bit.
again ‘1’ to the LOCK bit. This request to unlock the message buffer is always and immediately
granted, so the host does not have to check the state of the LOCK bit.
The host accesses the FIFO, receive message buffers, and transmit message buffers only through
the active receive FIFO buffer, the active receive message buffer, and the active transmit message
buffer.
The host must lock a buffer, to make it accessible through an active message buffer.
The host must unlock a message buffer when it has finished accessing it.
The host cannot access shadow message buffers.
The host cannot lock more than one receive message buffer and not more than one transmit
message buffer.
The host can lock up to three buffers mirrored to the appropriate active buffers at the same time —
one transmit message buffer, one receive message buffer, and one receive FIFO buffer.
The host may lock and unlock transmit and receive message buffers several times before
committing them.
The host may commit a transmit message buffer for transmission (by setting BUFCMT to ‘1’) after
performing several locking/unlocking procedures on that buffer before committing.
Unlocking the buffer in the FIFO will move the FIFO buffer access pointer to the next buffer in the
FIFO. Therefore, the FIFO does not support multiple consecutive locking/unlocking procedures for
one FIFO buffer.
The host cannot lock CC part buffers of double transmit message buffers.
The host can lock only the host part buffers of double transmit message buffers.
Once the buffer is locked, the host accesses it without checking the LOCK bit.
MFR4200 Data Sheet, Rev. 0
(CHIER)”), and may retry, if necessary.
Section 3.2.3.6.6, “Interrupt Status Register 0
Freescale Semiconductor
(ISR0)”).