mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 15

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Figure Number
Figure 3-57.
Figure 3-58.
Figure 3-59.
Figure 3-60.
Figure 3-61.
Figure 3-62.
Figure 3-63.
Figure 3-64.
Figure 3-65.
Figure 3-66.
Figure 3-67.
Figure 3-68.
Figure 3-69.
Figure 3-70.
Figure 3-71.
Figure 3-72.
Figure 3-73.
Figure 3-74.
Figure 3-75.
Figure 3-76.
Figure 3-77.
Figure 3-78.
Figure 3-79.
Figure 3-80.
Figure 3-81.
Figure 3-82.
Figure 3-83.
Figure 3-84.
Figure 3-85.
Figure 3-86.
Figure 3-87.
Figure 3-88.
Figure 3-89.
Figure 3-90.
Figure 3-91.
Freescale Semiconductor
Offset Correction Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Rate Correction Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Global Network Management Vector n Register, n = [0:5] . . . . . . . . . . . . . . . . . . . . . . . 96
Symbol Window Status Channel A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Symbol Window Status Channel B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Bus Guardian Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Startup Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Odd Cycles Without Clock Correction Fatal Register . . . . . . . . . . . . . . . . . 101
Maximum Odd Cycles Without Clock Correction Passive Register . . . . . . . . . . . . . . . 101
Channel Status Error Counter n Register, n = [0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Interrupt Enable Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Slot Status Selection n Register, n = [0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Slot Status Counter n Register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Slot Status Counter Condition n Register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Slot Status Counter Incrementation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Slot Status Counter Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Receive Buffer Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Transmit Buffer Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
CHI Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Clock Correction Failed Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Error Handling Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Interrupt Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Startup Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Slot Status n Register, n = [0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Odd Sync Frame ID n Register, n = [0:15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Even Sync Frame ID n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Odd Measurement Channel A n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Odd Measurement Channel B n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Even Measurement Channel A n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Even Measurement Channel B n Register, n = [0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Even Measurement Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Odd Measurement Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
FIFO Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Message Buffer Control, Configuration and Status n Register, n = [0:58] . . . . . . . . . . 126
Active Transmit Buffer Frame ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MFR4200 Data Sheet, Rev. 0
Title
Page
15