mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 117

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
SSINT — Slot Status Interrupt
This bit indicates that at least one slot status counter register SSCnR (see
Section 3.2.3.5.7, “Slot Status
Counter n Register, n = [0:7]
(SSCnR)”) that is enabled as an interrupt source via slot status counter
interrupt mask register SSCIMR (see
Section 3.2.3.5.10, “Slot Status Counter Interrupt Mask Register
(SSCIMR)”) has been incremented.
1 – At least one slot status counter that is enabled as an interrupt source has been incremented.
0 – No slot status counter that is enabled as an interrupt source has been incremented.
MRCE — Missing Rate Correction error
This bit is set if an insufficient number of measurement pairs is available for rate correction at the end of
the odd communication cycle.
1 – Insufficient number of measurement pairs available for rate correction
0 – Sufficient number of measurement pairs available for rate correction
EHLC — Error Handling Level Changed/ Startup Interrupt detected
This signal indicates, to the host, changes to the error handling level.
1 – Error handling level has changed.
0 – Error handling level has not changed.
MAXSYNC — Max Sync Frames Detected
The controller sets this bit when more than the configured maximum number of sync frames (see
Section 3.2.3.3.5, “Maximum Sync Frames Register
(MSFR)”) are detected within a single cycle. In this
case, the controller is not able to capture all time difference measurements.
1 – More than the configured maximum number of sync frames have been received.
0 – Not more than the configured maximum number of sync frames have been received.
CCLR — Clock Correction Limit Reached
This bit is set if offset or rate calculation reaches the threshold as configured in registers MOCR and
MRCR (see
Section 3.2.3.3.24, “Maximum Offset Correction Register
(MOCR)” and
Section 3.2.3.3.25,
“Maximum Rate Correction Register
(MRCR)”).
1 – Offset or rate calculation has reached the limit.
0 – Offset and rate correction are within the limit.
FATAL — Fatal Error
This bit is set if an illegal condition is detected in the protocol state machine; this can be caused by illegal
configuration. In this as, the controller goes into the diagnosis stop state immediately.
1 – Fatal error detected.
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
117