w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 9

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

2.6
The 16-bit Direct Register provides an address offset for all instructions using direct addressing. The
effective Direct Address is formed by adding the 8-bit instruction Direct Address field to the Direct Register.
The Direct Register is initialized to zero during Reset. The bank address for Direct Addressing is always
zero
2.7
There are two general purpose registers that are commonly referred to as Index Registers (X and Y) and
are frequently used as an index value for calculation of the effective address.
instruction with indexed addressing, the microprocessor fetches the opcode and the base address, and then
modifies the address by adding an Index Register contents to the address prior to performing the desired
operation. Pre-indexing or post-indexing of indirect addresses may be selected. In the Native mode (E=0),
both Index Registers are 16 bits wide where the Index Select Bit (X) of the Processor Status (P) register
equals zero. If the Index Select Bit (X) equals one, both registers will be 8 bits wide, and the high byte is
forced to zero.
2.8
The 8-bit Processor Status Register contains status flags and mode select bits. The Carry (C), Negative
(N), Overflow (V), and Zero (Z) status flags serve to report the status of most ALU operations. These status
flags are tested by use of Conditional Branch instructions.
Memory/Accumulator (M), and Index (X) bits are used as mode select flags. These flags are set by the
program to change microprocessor operations.
The Emulation (E) select and the Break (B) flags are accessible only through the Processor Status Register.
The Emulation mode select flag is selected by the Exchange Carry and Emulation Bits (XCE) instruction.
Table 8-1, W65C816S Compatibility Information, illustrates the features of the Native (E=0) and Emulation
(E=1) modes. The M and X flags are always equal to one in Emulation mode. When an interrupt occurs
during Emulation mode, the Break flag is written to stack memory as bit 4 of the Processor Status Register.
2.9
The 8-bit Program Bank Register holds the bank address for all instruction fetches. The 24-bit address
consists of the 16-bit instruction effective address and the 8-bit Program Bank address. The register value
is multiplexed with the data bus and presented on the Data bus lines during the first half of a program
memory cycle. The Program Bank Register is initialized to zero during Reset. The PHK instruction pushes
the PBR register onto the Stack.
2.10
The 16-bit Program Counter Register provides the addresses which are used to step the microprocessor
through sequential 8-bit program instruction fields. The PC is incremented for each 8-bit instruction field that
is fetched from program memory.
2.11
The Stack Pointer is a 16-bit register which is used to indicate the next available location in the stack
memory area. It serves as the effective address in stack addressing modes as well as subroutine and
interrupt processing. The Stack Pointer provides simple implementation of nested subroutines and multiple-
level interrupts. During Emulation mode, the S High-order byte (SH) is always equal to one. The bank
address for all stack operations is Bank zero.
Direct (D)
Index (X and Y)
Processor Status Register (P)
Program Bank Register (PBR)
Program Counter (PC)
Stack Pointer (S)
The Decimal (D), IRQ Disable (I),
When executing an
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