w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 52

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

7.1
When in the Native mode, the Stack may use memory locations 000000 to 00FFFF. The effective address
of Stack, Stack Relative, and Stack Relative Indirect Indexed addressing modes will always be within this
range. In the Emulation mode, the Stack address range is 000100 to 0001FF. The following opcodes and
addressing modes will increment or decrement beyond this range when accessing two or three bytes: JSL,
JSR (a,x), PEA, PEI, PER, PHD, PLD, RTL
7.2
7.3
The Absolute Indexed addressing modes are used to address data outside the direct addressing range.
The W65C02S addressing range is 0000 to FFFF. Indexing from page FFXX may result in a 00YY data
fetch when using the W65C02S. In contrast, indexing from page ZZFFXX may result in ZZ+1,00YY when
using the W65C816S.
7.4
7.5
When VDA or VPA are high and during all write cycles, the Address Bus is always valid. VDA and VPA
should be used to qualify all memory cycles. Note that when VDA and VPA are both low, invalid addresses
may be generated. The Page and Bank addresses could also be invalid. This will be due to low byte
addition only. The cycle when only low byte addition occurs is an optional cycle for instructions which read
memory when the Index Register consists of 8 bits. This optional cycle becomes a standard cycle for the
Store instruction, all instructions using the 16-bit Index Register mode, and the Read-Modify-Write
instruction when using 8- or 16-bit Index Register modes.
Stack Addressing
Direct Addressing
Absolute Indexed Addressing
ABORTB Input
VDA and VPA Valid Memory Address Output Signals
7.2.1
The effective address generated by Direct; Direct,X and Direct,Y addressing modes will always be
in the Native mode range 000000 to 00FFFF. When in the Emulation mode, the direct addressing
range is 000000 to 0000FF, except for [Direct] and [Direct],Y addressing modes and the PEI
instruction which will increment from 0000FE or 0000FF into the Stack area.
7.2.2
00DH00 to 00DHFF, except for [Direct] and [Direct],Y addressing modes and the PEI instruction
which will increment from 00DHFE or 00DHFF into the next higher page.
7.2.3
000000 to 00FFFF.
7.4.1
low during the Abort Interrupt sequence, the Abort Interrupt will be aborted. It is not recommended
to abort the Abort Interrupt. The ABORTB internal latch is cleared during the second cycle of the
Abort Interrupt.
registers to be modified:
7.4.1.1 Read-Modify-Write: Processor status modified if ABORTB is asserted after a modify cycle.
7.4.1.2 RTI: Processor status modified if ABORTB is asserted after cycle 3.
7.4.1.3 IRQB, NMIB, ABORTB BRK, COP: When ABORTB is asserted after cycle 2, PBR and
DBR will become 00 (Emulation mode) or PBR will become 00 (Native mode).
7.4.2
asynchronous ABORTB's may cause undesirable results due to the above conditions
The Direct Addressing modes are often used to access memory registers and pointers.
When in the Emulation mode and DH is not equal to zero, the direct addressing range is
When in the Emulation mode and DL in not equal to zero, the direct addressing range is
ABORTB should be held low for a period not to exceed one cycle. Also, if ABORTB is held
The ABORT Interrupt has been designed for virtual memory systems. For this reason,
Asserting the ABORTB input after the following instruction cycles will cause
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