w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 7

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

1 INTRODUCTION
The W65C816S is a low power cost sensitive 8/16-bit microprocessor. The variable length instruction set
and manually optimized core size makes the W65C816S an excellent choice for low power System-on-Chip
(SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor
Company, provides packaged chips for evaluation or volume production. To aid in system development,
WDC provides a Professional Software Development Kit (ProSDK) that is available for free download on a
trial basis, see www.westerndesigncenter.com for more information.
The WDC W65C816S is a fully static CMOS 16-bit microprocessor featuring software compatibility* with the
8-bit NMOS and CMOS 6500-series predecessors.
megabytes. These devices offer the many advantages of CMOS technology, including increased noise
immunity, higher reliability, and greatly reduced power requirements. A software switch determines whether
the processor is in the 8-bit "emulation" mode, or in the native mode, thus allowing existing systems to use
the expanded features.
As shown in the W65C816S Processor Programming Model, Table 2-1, the Accumulator, ALU, X and Y
Index registers, and Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page
register augments the Direct Page addressing mode (formerly Zero Page addressing). Separate Program
Bank and Data Bank registers provide 24-bit memory addressing with segmented or linear addressing.
Four new signals provide the system designer with many options. The ABORTB input can interrupt the
currently executing instruction without modifying internal register, thus allowing virtual memory system
design. Valid Data Address (VDA) and Valid Program Address (VPA) outputs facilitate dual cache memory
by indicating whether a data segment or program segment is accessed. Modifying a vector is made easy by
monitoring the Vector Pull (VPB) output.
•
consumption and increased noise immunity
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5%, 3.0+/- 5%, 3.3+/- 10%, 5.0+/- 5% specified for
use with advanced low voltage peripherals
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software compatibility with 65xx designs
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of memory space
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Index Registers
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Address (VPA) output for dual cache and cycle steal
DMA implementation
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vectors are being addressed
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supports processor repairs of bus error conditions
*
W65C816S
1.1
Except for the BBRx, BBSx, RMBx, and SMBx bit manipulation instructions which do not exist for the
Advanced fully static CMOS design for low power
Wide operating voltage range, 1.8+/- 5%, 2.5+/-
Emulation mode allows complete hardware and
24-bit address bus provides access to 16 MBytes
Full 16-bit ALU, Accumulator, Stack Pointer and
Valid Data Address (VDA) and Valid Program
Vector Pull (VPB) output indicates when interrupt
Abort (ABORTB) input and associated vector
Features of the W65C816S
The W65C816S extends addressing to a full 16
•
•
program segmentation or full 16 MByte linear
addressing
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provides capability for re-entrant, re-cursive and re-
locatable programming
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modes with 92 instructions using 256 opcodes
•
instructions
decrease interrupt latency and allows synchronization
with external events
•
vector supports co-processor configurations, i.e.,
floating point processors
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Low power consumption (300uA@1MHz)
Separate program and data bank registers allow
New Direct Register and stack relative addressing
24 addressing modes - 13 original W65C02S
Wait for Interrupt (WAI) and Stop-the-Clock (STP)
Co-Processor (COP) instruction with associated
Block move ability
further
reduce
power
consumption,
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