w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 43

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w65c816s

Manufacturer Part Number
w65c816s
Description
W65c816s 8/16?bit Microprocessor
Manufacturer
Western Design Center, Inc.
Datasheet
20. Relative r
BCC, BCS, BEQ, BMI, BNE, BPL, BRA,
BVC,BVS
9 OpCodes, 2 bytes, 2,3 and 4 cycles
21. Relative Long rl
BRL
1 OpCode, 3 bytes, 4 cycles
22a. Stack s
ABORT, IRQ, NMI, RES
4 hardware interrupts
0 bytes, 7 and 8 cycles
22b. Stack s
PLA, PLB, PLD, PLP, PLX, PLY
Different than N6502
6 Op Codes,1 byte, 4 and 5 cycles
22c. Stack s
PHA, PHB PHP, PHD, PHK, PHX, PHY
7 Op Codes, 1 byte, 3 and 4 cycles
22d. Stack s
PEA
1 Op Code, 3 bytes, 5 cycles
22e. Stack s
PEI
1 Op Code, 2 bytes, 6 and 7 cycles
22f. Stack s
PER
1 Op Code, 3 bytes, 6 cycles
Address Mode
(5)
(6)
(3)
(7)
(10)
(10)
(10)
(11)
(1)
(1)
(12)
(2)
Note
1
2
2a
2b
1
1
2
3
4
1
1
2
3
4
5
6
7
8
1
1
2
3
4
4a
1
2
3a
3
1
2
3
4
5
1
2
2a
3
4
5
6
1
2
3
4
5
6
Cycle
Table 5-7 (continued)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VPB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MLB
1
0
0
0
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1
VDA
(14)
1
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
VPA
(14)
PBR,PC
PBR,PC+1
PBR,PC+1
PBR,PC+1
PBR,PC+Offset
PBR,PC
PBR,PC+1
PBR,PC+2
PBR,PC+2
PBR,PC+Offset
PBR,PC
PBR,PC
0,S
0,S-1
0,S-2
0.S-3
0,VA
0,VA+1
0,AAV
PBR,PC
PBR,PC+1
PBR,PC+1
0,S+1
0,S+2
PBR,PC
PBR,PC+1
0,S
0,S-1
PBR,PC
PBR,PC+1
PBR,PC+2
0,S
0,S-1
PBR,PC
PBR,PC+1
PBR,PC+1
0,D+DO
0,D+DO+1
0,S
0,S-1
PBR,PC
PBR,PC+1
PBR,PC+2
PBR,PC+2
0,S
0,S-1
Address Bus
(15)
OpCode
Offset
IO
IO
OpCode
OpCode
Offset Low
Offset High
IO
OpCode
IO
IO
PBR
PCH
PCL
P
AAVL
AAVH
Next OpCode
OpCode
IO
IO
REG Low
REG High
OpCode
IO
REG High
REG Low
OpCode
AAL
AAH
AAH
AAL
OpCode
DO
IO
AAL
AAH
AAH
AAL
OpCode
Offset Low
Offset High
IO
PCH+Offset+Carry
PCL+Offset
Data Bus
43
RWB
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
0

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