w65c816s Western Design Center, Inc., w65c816s Datasheet - Page 51

• Manufacturer Part Number: w65c816s
• Description: W65c816s 8/16?bit Microprocessor
• Manufacturer: Western Design Center, Inc.

7 Caveats
Compatibility Issue
S (Stack)
X (X Index Reg)
Y (Y Index Reg)
A (Accumulator)
(Flag Reg)
Timing
A.ABS,X,ASL,LSR,
ROL
with
Crossing
B. Jump Indirect
Operand =XXFF
C.
Page
D. Decimal Mode
BRK Vector
Interrupt or Break
Bank Address
Memory Lock (ML)
Indexed
Page
(d),y a,x a,y
RDY Pulled during
Write Cycle
Branch
no
Boundary
Across
Across
Page
Always Page 1, 8
bits
Always Page 0
Always less than
256 ie 8 Bits
Always Page 0
Always less than
256 ie 8 Bits
8 bits
N, V and Z flags
invalid
mode.
D=unknown
reset. D not modified
after interrupt
7 cycles
5
invalid
crossing
4 cycles
No add. cycles
FFFE,F BRK bit=0 on
stack if IRQ, NMI
Not available
Not available
Extra
invalid address
Ignored
NMOS 6502
cycles
in
read
decimal
page
after
and
of
Table 7-1 Caveats
Always Page 1, 8
bits
Always Page 0
Always less than
256 ie 8 Bits
Always Page 0
Always less than
256 ie 8 Bits
8 bits
N,V and Z flags valid
in decimal mode. D=0
after reset/interrupt
6 cycles
6 cycles
4 cycles
Add 1 cycle
FFFE,F BRK bit=0 on
stack if IRQ, NMI
Not available
MLB=0
Modify and Write
cycles
Extra read of last
instruction fetch
Processor stops
W65C02
during
Always page 1, 8
bits
Always Page 0
Always less than
256 ie 8 Bits
Always Page 0
Always less than
256 ie 8 Bits
8 bits
N,V and Z flags valid
in decimal mode. D=0
after reset/interrupt
6 cycles
6 cycles
4 cycles
Add 1 Cycle
FFFE,F BRK bit=0 on
stack if IRQ, NMI
Not available
MLB=0
Modify and Write
cycles
Extra read of last
instruction fetch
Processor stops
W65C02S
during
Always page 1 8 bits
when(E=1), 16 bits
when E=0
Indexed page zero
always in page 0
(E=1), Cross page
(E=0)
Indexed page zero
always in page 0
(E=1), Cross page
(E=0)
8 bits (M=1), 16 bits
(M=0)
N,V and Z flags valid in
decimal mode. D=0 after
reset/interrupt
7 cycles
5 cycles
4 cycles
No add. cycles
00FFFE,F(E=1)
bit=0 on stack if IRQ-
NMIB, ABORTB
000FFE6,7 (E=0), X=X on
stack always
PBR not pushed (E=1)
RTI, PBR, not pulled
(E-1) PRB pushed (E=0)
RTI, PBR pulled (E=0)
MLB=0 during Read
Modify
cycles
Extra read of invalid
address
Processor Stops
W65C816S
and
Write
BRK
51