w65c21 Western Design Center, Inc., w65c21 Datasheet
w65c21
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w65c21 Summary of contents
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... June 19, 2009 W65C21 (W65C21N and W65C21S) Peripheral Interface Adapter (PIA) ...
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... The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright (C) 1981-2009 by The Western Design Center, Inc. All rights reserved, including the right of reproduction in whole or in part in any form. 2 ...
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... INTRODUCTION The WDC W65C21 (W65C21N and W65C21S very flexible Peripheral Interface Adapter (PIA) for use with WDC’s 65xx, 68xx, and other 8-bit microprocessor families. The W65C21 provides programmed microprocessor control two peripheral devices (Port A and Port B). Peripheral device control is accomplished through two 8-bit bidirectional I/O Ports, with individually designed Data Direction Registers ...
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... INPUT SELECT & CON TRO L CONTROL RWB REGISTER B (CRB ) PHI2 RESB IRQBB Figure 3 W65C21 PIA Block Diagram Figure 4 Interface Signals Relationship CA1 INTERUPT STATU S CONTROL A (ISCA) CA2 DA TA DIRECTION REG ISTER A (DD RA) PA0 PA1 PERIPHERAL PA2 PA3 ...
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ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Value Supply Voltage -0 Input Voltage V -0 Output Voltage V -0 OUT Operating Temp. - Range - Industrial Storage -55 to ...
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... W65C21N DC CHARACTERISTICS (V = 5. Parameter Input High Voltage Input Low Voltage Input Leakage Current CA1, CB1, CS0, CS1, CS2B, RESB, RS0, RS1, RWB , PHI2 Three-State (Off State), Leakage Current D0-D7, PB0-PB7, CB2 Input High Current PA0-PA7, CA2 Input Low Current PA0-PA7, CA2 ...
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... W65C21S DC CHARACTERISTICS (V = 5. Parameter Input High Voltage Input Low Voltage Input Leakage Current CA1, CB1, CS0, CS1, CS2B, RESB, RS0, RS1, RWB , PHI2 Three-State (Off State), Leakage Current D0-D7, PB0-PB7, CB2 Input High Current PA0-PA7, CA2 Input Low Current PA0-PA7, CA2 ...
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AC TIMING CHARACTERISTICS Parameter Symbol PHI2 Cycle t CYC PHI2 Pulse Width PHI2 Rise and Fall Time t rc READ TIMING Parameter Symbol Address Set-Up Time t ACR Address Hold Time t CAR Peripheral Data Setup Time t PCR Data ...
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PHI2 t ACW RS0, RS1, CS0, CS1, CS2B RWB t DCW D0-D7 DATA IN PA0-PA7 PB0-PB7 t CDR CB2 (PULSE OUT) CB1 CB2 (HANDSHAKE) Figure 5 Read Timing Waveforms t CYC CAW ...
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PHI2 t ACR RS0, RS1, CSO, CS1, CS2B t PCR PA0-PA7 PB0-PB7 t CDR D0-D7 DATA IN CA2 (PULSE OUT) CA1 CA2 (HANDSHAKE) CA1,CA2 CB1,CB2 IRQAB, IRQBB IRQAB, IRQBB t CYC CAR ...
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... CONTROL BIT CRA- CRB REGISTER SELECTED 1 - Peripheral Interface Data Direction Register Control Register Peripheral Interface Data Direction Register Control Register B Table 2 Register Addressing Figure 9B Port B, CB2 Buffers – W65C21N P P PIN N Figure 10B Port B, CB2 Buffers – W65C21S 11 ...
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... The eight bidirectional data bus lines are used to transfer data between the W65C21 and the microprocessor. During a Read operation, the contents of the W65C21 internal Data Bus Buffer (DBB) are transferred to the microprocessor via the Data Bus lines. During a Write operation, the Data Bus lines represent high impedance inputs over which data is transferred from the microprocessor to the Data Input Register (DIR) ...
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... Table 2. Full functionality is described under the Functional Description section for Register Access and Selection. RESET SIGNAL (RESB) A low signal (Logic 0) on the Reset line serves to initialize the W65C21, clearing all internal registers (to Logic 0) and placing all peripheral interface lines (PA and PB) in the input state. FUNCTIONAL DESCRIPTION The W65C21 PIA is organized into two independent sections referred to as the A Side and the B Side ...
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... DATA INPUT REGISTER (DIR) During a Write data operation, the microprocessor writes data into the W65C21 by placing data on the Data Bus. This data is then latched into the Data Input Register by the Phase Two (PHI2) clock. Once in the DIR, this data byte is transferred into one of six internal registers. This data transfer occurs after the trailing edge of the PHI2 clock pulse that latched the data into the DIR ...
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A second output mode allows CA2 to be used in conjunction with CA1 to “handshake” between the processor and the peripheral device. On the A side, this technique allows positive control of data transfers from the peripheral device into the ...
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... VCC for logic 1. The pull down transistors can sink a full 3.2 mA, making these buffers capable of driving two standard TTL loads. In the input mode, the W65C21S input pull-up transistors are connected to the I/O pin and will supply 50uA minimum pull-up current while the W65C22N will pull up greater than -200uA to drive two standard TTL loads ...
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... PB0-PB7) when clamping an output on the W65C21S. This does not apply to the W65C21N For the W65C21S only, the Port A input buffers supply 50 uA pull-up current at 2.4V when in the input mode and can supply the same drive current as the Port B buffers when in the output mode. The changes ...
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CRA (CRB) ACTIVE TRANSITION OF BIT 1 BIT 0 INPUT SIGNAL Negative 0 1 Negative 1 0 Positive 1 1 Positive *Note: Bit 7 of CRA (CRB) will be set to a Logic active transition ...
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DIM MIN A 51.69 B 13.72 C 3.94 D 0.36 E 1.02 F 2.54 G 1.65 H 0.20 J 15. 0.51 M 2.92 Figure 9 Package Dimensions 40-Pin Plastic Dip ...
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... Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. 2. Handle MOS parts only at conductive workstations. 3. Ground all assembly and repair tools. ORDERING INFORMATION W65C21N6TPLG-14 2166 East Brown Road Mesa, Arizona 85213 USA Fax: 480-835-6442 W65C 21N 6T ...